ENVIRONMENTAL MONITORING SYSTEM USING ZIGBEE

ABBREVATIONS

Symbol	Name
MAM	Memory  accelerometer module
VIC	Vectored interrupt controller
FIQ	Fast interrupt request
PWM	Pulse width modulation
GPIO	General purpose input/output
UART	Universal asynchronous receiver/transmitter
DLAB	Data latch access bit
LCR	Line control register
LSR	Line status register
RDR	Receiver data ready
SPI	Serial peripheral interface
ADC	Analog to digital converter
DAC	Digital to analog converter
SSP	Synchronous serial port
MOSI	Master out slave in
RTC	Real time clock
EINT	External interrupt
DTR	Data terminal ready
AHB	Advanced high performance
ATLE	Auto transfer length extraction
CTS	Clear to send
RTS	Request to send
DSR	Data set ready
RI	Ring indicator

INTRODUCTION

An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few predefined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale.

 Personal digital assistants (PDAs) or handheld computers are generally considered embedded devices because of the nature of their hardware design, even though they are more expandable in software terms. This line of definition continues to blur as devices expand. With the introduction of the OQO Model 2 with the Windows XP operating system and ports such as a USB port — both features usually belong to “general purpose computers”, — the line of nomenclature blurs even more.

Embedded systems plays major role in electronics varies from portable devices to large stationary installations like digital watches and MP3 players, traffic lights, factory controllers, or the systems controlling nuclear power plants.

In terms of complexity embedded systems can range from very simple with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure.

Examples of Embedded Systems:

• Avionics, such as inertial guidance systems, flight control hardware/software and other integrated systems in aircraft and missiles
• Cellular telephones and telephone switches
• Engine controllers and antilock brake controllers for automobiles
• Home automation products, such as thermostats, air conditioners, sprinklers, and security monitoring systems
• Handheld calculators
• Handheld computers
• Household appliances, including microwave ovens, washing machines, television sets, DVD players and recorders
• Medical equipment
• Personal digital assistant
• Videogame consoles
• Computer peripherals such as routers and printers.
• Industrial controllers for remote machine operation.

 

 

 

 

 

 

 

BLOCK DIAGRAM DESCRIPTION

Power Supply: This section is meant for supplying Power to all the sections mentioned above.It basically consists of a Transformer to step down the 230V ac to 9V ac followed by diodes. Here diodes are used to rectify the ac to dc. After rectification the obtained rippled dc is filtered using a capacitor Filter. A positive voltage regulator is used to regulate the obtained dc voltage.

Microcontroller: This section forms the control unit of the whole project. This section basically consists of a Microcontroller with its associated circuitry like Crystal with capacitors, Reset circuitry, Pull up resistors (if needed) and so on. The Microcontroller forms the heart of the project because it controls the devices being interfaced and communicates with the devices according to the program being written.

MAX 232: The microcontroller can communicate with the serial devices using its single Serial Port. The logic levels at which this serial port operates is TTL logics. But some of the serial devices operate at RS 232 Logic levels. For example PC and GSM etc. So in order to communicate the Microcontroller with either GSM modem or PC, a mismatch between the Logic levels occurs. In order to avoid this mismatch, in other words to match the Logic levels, a Serial driver is used. And MAX 232 is a Serial Line Driver used to establish communication between microcontroller and PC (or GSM)

LCD Display: This section is basically meant to show up the status of the project. This project makes use of Liquid Crystal Display to display / prompt for necessary information.

Temperature sensor: Thermistors are a temperature sensing devise. It is used to sense the temperature. In this project by depends on the value of temperature the exhaust fan will run.

Smoke sensor:  Smoke sensor is used to detect any leakage of smoke and any hazardous gases such that an alarm can be initiated to avoid any damages in the industries. These sensors are also used in many applications like corporate and in any office work areas these are linked to fire alarms

LDR: The LDR is used to measure the light intensity.

Humidity sensor: Humidity sensor is a device that measures the relative humidity of in a given area. A humidity sensor can be used in both indoors and outdoors. Humidity sensors are available in both analog and digital forms.

ZIGBEE: Zigbee is new wireless technology guided by IEEE 802.15.4 Personal Area Network standard. It is primarily designed for the wide ranging controlling applications and to replace the existing non-standard technologies. It currently operates in 868MHz band at a data rate of 20Kbps in Europe, 914MHz band at 40kbps in USA, and the 2.4GHz ISM bands Worldwide at a maximum data-rate of 250kbps.

SCHEMATIC

SCHEMATIC DESCRIPTION:

Firstly, the required operating voltage for Microcontroller AT89S52 is 5V. Hence the 5V D.C. power supply is needed by the same. This regulated 5V is generated by first stepping down the 230V to 18V by the step down transformer.

In the both the Power supplies the step downed a.c. voltage is being rectified by the Bridge Rectifier. The diodes used are 1N4007. The rectified a.c voltage is now filtered using a ‘C’ filter. Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator. This voltage regulator allows us to have a Regulated Voltage. In Power supply given to Microcontroller 5V is generated using 7805 and in other two power supply 12V is generated using 7812. The rectified; filtered and regulated voltage is again filtered for ripples using an electrolytic capacitor 100μF. Now the output from the first section is fed to 40^th pin of AT89S52 microcontroller to supply operating voltage and from other power supply to circuitry.

The microcontroller AT89S52 with Pull up resistors at Port0 and crystal oscillator of 11.0592 MHz crystal in conjunction with couple of capacitors of  is placed at 18^th & 19^th pins of AT89S52 to make it work (execute) properly.

Port 0:

P0 is connected to the data pins of the LCD.

PORT 2:

P2.5, P2.6, P2.7 are connected to control pins of the LCD.

Port 3:

20^th is connected to GROUND

40^th is connected to Vcc

 

HARDWARE COMPONENTS

Microcontroller (AT89S52):

8-bit Microcontroller with 8K Bytes

In-System Programmable Flash

Features

• Compatible with MCS-51® Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry- standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit  timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,

and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash  programming and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this  application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and  verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external

timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash  programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT89S52 SFR Map and Reset Values

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

Watchdog Timer

(One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external

clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot

be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.  To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user

should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52..

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external  input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition,

the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least

once before it changes, the level should be held for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L,  respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,

like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.  A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 8. The baud rate generator mode is similar to the auto-reload

mode, in that a rollover in TH2 causes  the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation.

The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it  increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as

an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is

incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be  read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 9. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.

Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the  Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 12. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Figure 11. Oscillator Connections

Program Memory Lock Bits

The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.

Programming the Flash – Parallel Mode

The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89S52 code memory array is programmed byte-bybyte.

Programming Algorithm: Before programming the AT89S52, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S52, take the following

steps:

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is

self-timed and typically takes no more than 50 μs. Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the object file is reached.

Data Polling: The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be  verified directly by reading them back.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 52H indicates 89S52

(200H) = 06H

Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns – 500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.

Programming the Flash – Serial Mode

The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the  Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz.

Serial Programming Algorithm

To program and verify the AT89S52 in the serial programming mode, the following sequence is recommended:

1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”.If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds.

2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1  divided by 16.

3. The Code array is programmed one byte at a time by supplying the address and data together with the

appropriate Write instruction. The write cycle is selftimed and typically takes less than 1 ms at 5V.

4. Any memory location can be verified by using the Read instruction which returns the content at the

selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal device operation.

Power-off sequence (if needed):

Set XTAL1 to “L” (if a crystal is not used).

Set RST to “L”.

Turn VCC power off.

Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO.

Serial Programming Instruction Set

The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 10.

Programming Interface – Parallel Mode

Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1. For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256

bytes are shifted in/out. Then the next instruction will be ready to be decoded.

Power Supply:

The power supply is designed to convert high voltage AC mains electricity to a suitable low voltage supply for electronic circuits and other devices. A power supply can by broken down into a series of blocks, each of which performs a particular function. A D.C. power supply which maintains the output voltage constant irrespective of a.c mains fluctuations or load variations is known as “Regulated D.C Power Supply”

For example a 5V regulated power supply system as shown below:

Fig : Functional Block Diagram of Power supply

Transformer:

A transformer is an electrical device which is used to convert electrical power from one electrical circuit to another without change in frequency.

Transformers convert AC electricity from one voltage to another with little loss of power. Transformers work only with AC and this is one of the reasons why mains electricity is AC.  Step-up transformers increase in output voltage, step-down transformers decrease in output voltage. Most power supplies use a step-down transformer to reduce the dangerously high mains voltage to a safer low voltage.   The input coil is called the primary and the output coil is called the secondary. There is no electrical connection between the two coils; instead they are linked by an alternating magnetic field created in the soft-iron core of the transformer. The two lines in the middle of the circuit symbol represent the core.   Transformers waste very little power so the power out is (almost) equal to the power in. Note that as voltage is stepped down current is stepped up.   The ratio of the number of turns on each coil, called the turn’s ratio, determines the ratio of the voltages. A step-down transformer has a large number of turns on its primary (input) coil which is connected to the high voltage mains supply, and a small number of turns on its secondary (output) coil to give a low output voltage.

Fig : An Electrical Transformer

Turns ratio = Vp/ V_S = Np/N_S

Power Out= Power In

V_S X I_S=V_P X I_P

Vp = primary (input) voltage
Np = number of turns on primary coil
Ip  = primary (input) current

Rectifier:

A circuit, which is used to convert a.c to dc, is known as RECTIFIER. The process of conversion a.c to d.c is called “rectification”

Types of Rectifiers:

• Half wave Rectifier
• Full wave rectifier

1. Center tap full wave rectifier.

2. Bridge type full bridge rectifier.

Full-wave Rectifier:

From the above comparisons we came to know that full wave bridge rectifier as more advantages than the other two rectifiers. So, in our project we are using full wave bridge rectifier circuit.

Bridge Rectifier:

A bridge rectifier makes use of four diodes in a bridge arrangement to achieve full-wave rectification. This is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally.

   A bridge rectifier makes use of four diodes in a bridge arrangement as shown in fig(a) to achieve full-wave rectification. This is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally.

Fig(24.A):

Operation:

During positive half cycle of secondary, the diodes D2 and D3 are in forward biased while D1 and D4 are in reverse biased as shown in the fig(b). The  current flow direction is shown in the fig (b) with dotted arrows.

Fig(24.B)

During negative half cycle of secondary voltage, the diodes D1 and D4 are in forward biased while D2 and D3 are in reverse biased as shown in the fig(c). The  current flow direction is shown in the fig (c) with dotted arrows.

Fig(24.C)

Filter:

A Filter is a device, which removes the a.c component of rectifier output but allows the d.c component to reach the load.

Capacitor Filter:

We have seen that the ripple content in the rectified output of half wave rectifier is 121% or that of full-wave or bridge rectifier or bridge rectifier is 48% such high percentages of ripples is not acceptable for most of the applications. Ripples can be removed by one of the following methods of filtering:

(a) A capacitor, in parallel to the load, provides an easier by –pass for the ripples voltage though it due to low impedance. At ripple frequency and leave the d.c.to appears the load.

(b) An inductor, in series with the load, prevents the passage of the ripple current (due to high impedance at ripple frequency) while allowing the d.c (due to low resistance to d.c)

(c) various combinations of capacitor  and inductor, such  as L-section  filter   section filter, multiple section filter etc. which make use of  both the properties mentioned in (a) and (b) above. Two cases of capacitor filter, one applied on half wave rectifier and another with full wave rectifier.

Filtering is performed by a large value electrolytic capacitor connected across the DC supply to act as a reservoir, supplying current to the output when the varying DC voltage from the rectifier is falling. The capacitor charges quickly near the peak of the varying DC, and then discharges as it supplies current to the output. Filtering significantly increases the average DC voltage to almost the peak value (1.4 × RMS value).

To calculate the value of capacitor(C),

C = ¼*√3*f*r*Rl

Where,

f = supply frequency,

r = ripple factor,

Rl = load resistance

Note: In our circuit we are using 1000microfarads.

Parameter	Type of Rectifier
	Half wave                                Full wave             Bridge
Number of   diodes	1	2	3
PIV of diodes	Vm	2Vm	Vm
D.C output voltage	Vm/	2Vm/	2Vm/
Vdc, at  no-load	0.318Vm	0.636Vm	0.636Vm
Ripple factor	1.21	0.482	0.482
Ripple  frequency	f	2f	2f
Rectification  efficiency	0.406	0.812	0.812
Transformer  Utilization Factor(TUF)	0.287	0.693	0.812
RMS voltage Vrms	Vm/2	Vm/√2	Vm/√2

Table: Comparison of rectifier circuits:

Regulator:

Voltage regulator ICs is available with fixed (typically 5, 12 and 15V) or variable output voltages. The maximum current they can pass also rates them. Negative voltage regulators are available, mainly for use in dual supplies. Most regulators include some automatic protection from excessive current (‘overload protection’) and overheating (‘thermal protection’).  Many of the fixed voltage regulator ICs have 3 leads and look like power transistors, such as the 7805 +5V 1A regulator shown on the right. The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then when you turn on the power, you get a 5 volt supply from the output pin.

Fig 25: A Three Terminal Voltage Regulator

78XX:

The Bay Linear LM78XX is integrated linear positive regulator with three terminals. The LM78XX offer several fixed output voltages making them useful in wide range of applications. When used as a zener diode/resistor combination replacement, the LM78XX usually results in an effective output impedance improvement of two orders of magnitude, lower quiescent current. The LM78XX is available in the TO-252, TO-220 & TO-263packages,

Features:

• Output Current of 1.5A

• Output Voltage Tolerance of 5%

• Internal thermal overload protection

• Internal Short-Circuit Limited

• No External Component

• Output Voltage 5.0V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 24V

• Offer in plastic TO-252, TO-220 & TO-263

• Direct Replacement for LM78XX

Liquid crystal display

Liquid crystal displays (LCDs) have materials, which combine the properties of both liquids and crystals. Rather than having a melting point, they have a temperature range within which the molecules are almost as mobile as they would be in a liquid, but are grouped together in an ordered form similar to a crystal.

An LCD consists of two glass panels, with the liquid crystal material sand witched in between them. The inner surface of the glass plates are coated with transparent electrodes which define the character, symbols or patterns to be displayed polymeric layers are present in between the electrodes and the liquid crystal, which makes the liquid crystal molecules to maintain a defined orientation angle.

One each polarisers are pasted outside the two glass panels. These polarisers would rotate the light rays passing through them to a definite angle, in a particular direction.

When the LCD is in the off state, light rays are rotated by the two polarisers and the liquid crystal, such that the light rays come out of the LCD without any orientation, and hence the LCD appears transparent.

When sufficient voltage is applied to the electrodes, the liquid crystal molecules would be aligned in a specific direction. The light rays passing through the LCD would be rotated by the polarisers, which would result in activating/ highlighting the desired characters.

The LCD’s are lightweight with only a few millimeters thickness. Since the LCD’s consume less power, they are compatible with low power electronic circuits, and can be powered for long durations.

The LCD’s don’t generate light and so light is needed to read the display. By using backlighting, reading is possible in the dark. The LCD’s have long life and a wide operating temperature range.

Changing the display size or the layout size is relatively simple which makes the LCD’s more customers friendly.

The LCDs used exclusively in watches, calculators and measuring instruments are the simple seven-segment displays, having a limited amount of numeric data. The recent advances in technology have resulted in better legibility, more information displaying capability and a wider temperature range. These have resulted in the LCDs being extensively used in telecommunications and entertainment electronics. The LCDs have even started replacing the cathode ray tubes (CRTs) used for the display of text and graphics, and also in small TV applications.

This section describes the operation modes of  LCD’s then describe how to program and interface an LCD to 8051 using Assembly and C.

LCD operation

In recent years the LCD is finding widespread use replacing LEDs(seven-segment LEDs  or other multisegment LEDs).This is due to the following reasons:

1.  The declining prices of LCDs.

2.  The ability to display numbers, characters and graphics. This is in                                 contract to LEDs, which are  limited to numbers and a few characters.

3.  Incorporation of a refreshing controller into the LCD, there by

relieving the CPU of the task of refreshing the LCD. In the contrast,

the LED must be refreshed by the CPU to keep  displaying the data.

4.  Ease of programming for characters and graphics.

LCD pin description

The LCD discussed in this section has 14 pins. The function of each pins is given in table.

 

 

 

TABLE 1:Pin description for LCD:

Pin	symbol	I/O	Description
1	Vss	—	Ground
2	Vcc	—	+5V power supply
3	VEE	—	Power supply to control contrast
4	RS	I	RS=0 to select command register  RS=1 to select data register
5	R/W	I	R/W=0 for write  R/W=1 for  read
6	E	I/O	Enable
7	DB0	I/O	The 8-bit data bus
8	DB1	I/O	The 8-bit data bus
9	DB2	I/O	The 8-bit data bus
10	DB3	I/O	The 8-bit data bus
11	DB4	I/O	The 8-bit data bus
12	DB5	I/O	The 8-bit data bus
13	DB6	I/O	The 8-bit data bus
14	DB7	I/O	The 8-bit data bus

TABLE 2: LCD Command Codes

Code  (hex)	Command to LCD Instruction  Register
1	Clear display screen
2	Return home
4	Decrement cursor
6	Increment cursor
5	Shift display right
7	Shift display left
8	Display off, cursor off
A	Display off, cursor on
C	Display on, cursor off
E	Display on, cursor on
F	Display on, cursor blinking
10	Shift cursor position to left
14	Shift cursor position to right
18	Shift the entire display to the left
1C	Shift the entire display to the right
80	Force cursor to beginning of 1st line
C0	Force cursor to beginning of 2nd line
38	2 lines and 5×7 matrix

Uses:

The LCDs used exclusively in watches, calculators and measuring instruments are the simple seven-segment displays, having a limited amount of numeric data. The recent advances in technology have resulted in better legibility, more information displaying capability and a wider temperature range. These have resulted in the LCDs being extensively used in telecommunications and entertainment electronics. The LCDs have even started replacing the cathode ray tubes (CRTs) used for the display of text and graphics, and also in small TV applications.

LCD INTERFACING

Sending commands and data to LCDs with a time delay:

Fig 21: Interfacing of LCD to a micro controller

To send any command from table 2 to the LCD, make pin RS=0. For data, make RS=1.Then send a high –to-low  pulse to the E pin to enable the internal latch of the LCD.

TEMPERATURE SENSOR (TMP103):

The TMP103 is a analog output temperature sensor in a four-ball wafer chip-scale package (WCSP). The TMP103 is capable of reading temperatures to a resolution of 1°C. The TMP103 features a two-wire interface that is compatible with both I²C and SMBus interfaces. In addition, the interface supports multiple device access (MDA) commands that allow the master to communicate with multiple devices on the bus simultaneously, eliminating the need to send individual commands to each TMP103 on the bus. Up to eight TMP103s can be tied together in parallel and easily read by the host. The TMP103 is especially ideal for space-constrained, power-sensitive applications with multiple temperature measurement zones that must be monitored. The TMP103 is specified for operation over a temperature range of –40°C to +125°C.

Features:

• Multiple Device Access (MDA):
  • Global Read/Write Operations
• I²C™-/SMBus™-Compatible Interface
• Resolution: 8 Bits
• Accuracy: ±1°C Typ (–10°C to +100°C)
• Low Quiescent Current:
  • 3µA Active I_Q at 0.25Hz
  • 1µA Shutdown
• Supply Range: 1.4V to 3.6V
• Digital Output
• Package: 4-Ball WCSP (DSBGA)

Applications:

• Handsets
• Notebooks

Fig: TMP103

LIGHT DEPENDENT RESISTORS

LDRs or Light Dependent Resistors are very useful especially in light/dark sensor circuits. Normally the resistance of an LDR is very high, sometimes as high as 1000 000 ohms, but when they are illuminated with light resistance drops dramatically.

The animation opposite shows that when the torch is turned on, the resistance of the LDR falls, allowing current to pass through it.
Circuit Wizard software has been used to display, the range of values of a ORP12, LDR.  When a light level of 1000 lux (bright light) is directed towards it, the resistance is 400R (ohms). When a light level of 10 lux (very low light level) is directed towards it, the resistance has risen dramatically to 10.43M (10430000 ohms).

The general purpose photoconductive cell is also known as LDR – light dependent resistor. It is a type of semiconductor and its conductivity changes with proportional change in the intensity of light. The complete principle of an LDR is as follows. In a semiconductor an energy gap exists between conduction electrons and valence electrons. As an LDR is also known as semiconductor photo-conductive transducer, when light is incident on it, a photon is absorbed and thereby it excites an electron from valence band into conduction band. Due to such new electrons coming up in conduction band area, the electrical resistance of the device decreases. Thus the LDR or photo-conductive transducer has the resistance which is the inverse function of radiation intensity.

Where, 

λ0 = threshold wavelength, in meters

e = charge on one electron, in Coulombs

Ew = work function of the metal used, in eV

Here we must note that any radiation with wavelength greater than the value obtained in above equation CANNOT PRODUCE any change in the resistance of this device.

Construction of a Light Dependent Resistor: there two common types of materials used to manufacture the photoconductive cells. They are Cadmium Sulphide (CdS) and Cadmium Selenide (CdSe).

The band gap energy of Cadmium Sulphide is 2.42eV and for Cadmium Selenide it is 1.74eV. Due to such large energy gaps, both the materials have extremely high resistivity at room temperature. Hence, these materials are widely used in LDR for practical purpose.

A long, thin and narrow strip of CdS is fixed on the surface of ceramic substrate in the form of zigzag wire as shown in following figure. This construction gives minimum area and maximum length. Then the structure is enclosed in round metallic or plastic case and two terminals (made up of either tin or indium) are taken out for external connections. The structure is covered with glass sheet to protect it from moisture and dust and allows only light to fall on it.

Characteristics of photoconductive cells

Photoconductor	Time Constant	Spectral Band
Cadmium Sulphide CdS	100 milli sec	0.47 to 0.72 um
Cadmium Selenide CdSe	10 milli sec	0.6 to 0.77 um
Lead Sulphide PbS	410 micro sec	1 to 3.2 um
Lead Selenide PbSe	10.2 micro sec	1.52 to 4.2 um

Now when the device is dark, its resistance is called as dark resistance. This resistance is typically of the order of 10¹³ ohms. When light falls on it, its resistance decreases up to several kilo ohms or even hundreds of ohms, depending on the intensity of light, falling on it. The spectral response characteristics of two commercial cells were compared in our laboratory. And we found that there is almost no response to the radiation of a wavelength which was shorter than 300nm. It was very interesting to note that the Cadmium Sulphide cell has a peak response nearer or within the green color of the spectrum within a range of 520nm. Thus it can be used nearer to the infra-red region up to 750nm. It was found that the maximum response of Cadmium Sulphoselenide is in the yellow-orange range at 615nm and also it can be used in the infra-red region up to about 970nm.

Mathematical analysis of photoconductive cell

The sensitivity of photoconductive transducer is defined as the ratio of change in resistance to the proportional change in the irradiation level. Thus, the spectral response of the sensor must match with the appropriate response from light source.

Mathematically –

Since the photoconductive cell has relatively large sensitive area, a small change in light intensity will cause a large change in its resistance. Generally, all photoconductive cells show the property of change in resistance in the ratio of 1000:1 for dark to light irradiance change of 0.005W/m² to 50W/m².

But it is also interesting to note that the the relation between irradiance and its resistance is NOT LINEAR. It is actually exponential relationship, as follows –

Where, R_f = dark resistance in ohms

R_i = final resistance when light is incident on it

R_t = resistance at any time (t)

and τ = standard time constant

Though this all discussion sounds good for a photoconductive cell i.e. an LDR, it has a disadvantage that when its temperature changes, its resistance changes drastically for a particular light intensity. Hence, this device is NOT SUITABLE for precise measurements in analog applications.

Fig: characteristics

Applications

•                   It is used in burglar alarm to give alarming sound when a burglar invades sensitive premises.
•             It is used in street light control to switch on the lights during dusk and switch off during dawn automatically.
• It is used in Lux meter to measure intensity of light in Lux.
• It is used in photo sensitive relay circuit.
• Two cadmium sulphide (cds) photoconductive cells with spectral responses similar to that of the human eye. The cell resistance falls with increasing light intensity. Applications include smoke detection, automatic lighting control, and batch counting and burglar alarm systems.

Fig: LDR

SMOKE SENSOR (MQ2):

Smoke sensor is used to detect any leakage of smoke and any hazardous gases such that an alarm can be initiated to avoid any damages in the industries. These sensors are also used in many applications like corporate and in any office work areas these are linked to fire alarms And buzzers through the micro-controller.

There are two main types of smoke detectors: Ionization detectors and photoelectric detectors. A smoke alarm uses one or both methods, sometimes plus a heat detector, to warn of a fire.

Ionization Detectors:

Ionization detectors have an ionization chamber and a source of ionizing radiation. The source of ionizing radiation is a minute quantity of americium-241 (perhaps 1/5000th of a gram), which is a source of alpha particles (helium nuclei). The ionization chamber consists of two plates separated by about a centimeter. The battery applies a voltage to the plates, charging one plate positive and the other plate negative. Alpha particles constantly released by the americium knock electrons off of the atoms in the air, ionizing the oxygen and nitrogen atoms in the chamber. The positively-charged oxygen and nitrogen atoms are attracted to the negative plate and the electrons are attracted to the positive plate, generating a small, continuous electric current. When smoke enters the ionization chamber, the smoke particles attach to the ions and neutralize them, so they do not reach the plate. The drop in current between the plates triggers the alarm.

Photoelectric Detectors

In one type of photoelectric device, smoke can block a light beam. In this case, the reduction in light reaching a photocell sets off the alarm. In the most common type of photoelectric unit, however, light is scattered by smoke particles onto a photocell, initiating an alarm. In this type of detector there is a T-shaped chamber with a light-emitting diode (LED) that shoots a beam of light across the horizontal bar of the T. A photocell, positioned at the bottom of the vertical base of the T, generates a current when it is exposed to light. Under smoke-free conditions, the light beam crosses the top of the T in an uninterrupted straight line, not striking the photocell positioned at a right angle below the beam. When smoke is present, the light is scattered by smoke particles, and some of the light is directed down the vertical part of the T to strike the photocell. When sufficient light hits the cell, the current triggers the alarm.

Both ionization and photoelectric detectors are effective smoke sensors. Both types of smoke detectors must pass the same test to be certified as UL smoke detectors. Ionization detectors respond more quickly to flaming fires with smaller fire particles; photoelectric detectors respond more quickly to smoldering fires. In either type of detector, steam or high humidity can lead to condensation on the circuit board and sensor, causing the alarm to sound. Ionization detectors are less expensive than photoelectric detectors, but some users purposely disable them because they are more likely to sound an alarm from normal cooking due to their sensitivity to minute smoke particles. However, ionization detectors have a degree of built-in security not inherent to photoelectric detectors. When the battery starts to fail in an ionization detector, the ion current falls and the alarm sounds, warning that it is time to change the battery before the detector becomes ineffective. Back-up batteries may be used for photoelectric detectors.

Sensitive material of MQ-3 gas sensor is SnO2, which with lower conductivity in clean air. When the target alcohol gas exist, The sensor’s conductivity is more higher along with the gas concentration rising. MQ-3 gas sensor has high sensitivity to Alcohol, and has good resistance to disturb of gasoline, smoke and vapor. The sensor could be used to detect alcohol with different concentration; it is with low cost and suitable for different application.

Good sensitivity to alcohol gas

Long life and low cost

Simple drive circuit

 

 

 

 

 

Basic test loop

The above is basic test circuit of the sensor. The sensor needs to be put 2 voltage, heater voltage and test voltage（VC）. VH used to supply certified working temperature to the sensor, while VC used to detect voltage (VRL) on load resistance whom is in series with sensor. The sensor has light polarity, Vc need DC power. VC and VH could use same power circuit with precondition to assure performance of sensor. In order to make the sensor with better performance, suitable RL value is needed:

Structure and configuration:

Structure and configuration of MQ-3 gas sensor is shown as Fig. 3, sensor composed by micro AL2O3 ceramic tube, Tin Dioxide (SnO2) sensitive layer, measuring electrode and heater are fixed into a crust made by plastic and stainless steel net. The heater provides necessary work conditions for work of sensitive components. The enveloped MQ-4 has 6 pin, 4 of them are used to fetch signals, and other 2 are used for providing heating current.

HUMIDITY:

Humidity is the amount of water vapor in the air. In daily language the term “humidity” is normally taken to mean relative humidity. Relative humidity is defined as the ratio of the partial pressure of water vapor in a parcel of air to the saturated vapor pressure of water vapor at a prescribed temperature. Humidity may also be expressed as absolute humidity and specific humidity. Relative humidity is an important metric used in forecasting weather. Humidity indicates the likelihood of precipitation, dew, or fog. High humidity makes people feel hotter outside in the summer because it reduces the effectiveness of sweating to cool the body by preventing the evaporation of perspiration from the skin.

Absolute humidity

Absolute humidity is the quantity of water in a particular volume of air. The most common units are grams per cubic meter, although any mass unit and any volume unit could be used.

Relative humidity

Relative humidity is defined as the ratio of the partial pressure of water vapor in a gaseous mixture of air and water vapor to the saturated vapor pressure of water at a given temperature. Relative humidity is expressed as a percentage.

Specific humidity

Specific humidity is the ratio of water vapor to air (including water vapor and dry air) in a particular volume. Measuring and regulating humidity

A hygrometer is a device used for measuring the humidity of the air

There are various devices used to measure and regulate humidity. A device used to measure humidity is called a psychrometer or hygrometer. A humidistat is used to regulate the humidity of a building with a de-humidifier. These can be analogous to a thermometer and thermostat for temperature control.

Humidity is also measured on a global scale using remotely placed satellites. These satellites are able to detect the concentration of water in the troposphere at altitudes between 4 and 12 kilometers. Satellites that can measure water vapor have sensors that are sensitive to infrared radiation. Water vapor specifically absorbs and re-radiates radiation in this spectral band. Satellite water vapor imagery plays an important role in monitoring climate conditions (like the formation of thunderstorms) and in the development of future weather forecasts.

Hygrometers are instruments used for measuring humidity. A simple form of a hygrometer is specifically known as a “psychrometer” and consists of two thermometers, one of which includes a dry bulb and the other of which includes a bulb that is kept wet to measure wet-bulb temperature. Evaporation from the wet bulb lowers the temperature, so that the wet-bulb thermometer usually shows a lower temperature than that of the dry-bulb thermometer, which measures dry-bulb temperature. When the air temperature is below freezing, however, the wet bulb is covered with a thin coating of ice and yet may be warmer than the dry bulb. Relative humidity is computed from the ambient temperature as shown by the dry-bulb thermometer and the difference in temperatures as shown by the wet-bulb and dry-bulb thermometers. Relative humidity can also be determined by locating the intersection of the wet- and dry-bulb temperatures on a psychrometric chart. One device that uses the wet/dry bulb method is the sling psychrometer, where the thermometers are attached to a handle or length of rope and spun around in the air for a few minutes.

Calibration

Accurate calibration of the thermometers used is of course fundamental to precise humidity determination by the wet-dry method; it is also important for the most accurate results to protect the thermometers from radiant heat and ensure a sufficiently high speed of airflow over the wet bulb. One of the most precise types of wet-dry bulb psychrometer was invented in the late 19th century by Adolph Richard Aßmann in English-language references the device is usually spelled “Assmann psychrometer.” In this device, each thermometer is suspended within a vertical tube of polished metal, and that tube is in turn suspended within a second metal tube of slightly larger diameter; these double tubes serve to isolate the thermometers from radiant heating. Air is drawn through the tubes with a fan that is driven by a clockwork mechanism to ensure a consistent speed (some modern versions use an electric fan with electronic speed control). According to Middleton, 1966, “an essential point is that air is drawn between the concentric tubes, as well as through the inner one.”

One solution sometimes used for accurate humidity measurement when the air temperature is below freezing is to use a thermostatically-controlled electric heater to raise the temperature of outside air to above freezing. In this arrangement, a fan draws outside air past (1) a thermometer to measure the ambient dry-bulb temperature, (2) the heating element, (3) a second thermometer to measure the dry-bulb temperature of the heated air, then finally (4) a wet-bulb thermometer. According to the WMO Guide, “The principle of the heated psychrometer is that the water vapour content of an air mass does not change if it is heated. This property may be exploited to the advantage of the psychrometer by avoiding the need to maintain an ice bulb under freezing conditions.” ^[4]. Since the humidity of the ambient air is calculated indirectly from three temperature measurements, in such a device accurate thermometer calibration is even more important than for a two-bulb configuration.

A sling psychrometer for outdoor use

Other types of hygrometers are also commonly used to determine the ambient humidity. Such devices frequently use a human or animal hair under tension. The traditional folk art device known as a “weather house” works on this principle. In order to see changes that occur over time, several hygrometers record the value of humidity on a piece of graduated paper so that the values can be read off the chart.

Works

A digital humidity sensor works via two micro sensors that are calibrated to the relative humidity of the given area. These are then converted into the digital format via an analog to digital conversion process which is done by a chip located in the same circuit. A machine made electrode based system made out of polymer is what makes up the capacitance for the sensor. This protects the sensor from user front panel (interface).

 

ZIGBEE TECHNOLOGY:

ZIGBEE is a new wireless technology guided by the IEEE 802.15.4 Personal Area Networks standard. It is primarily designed for the wide ranging automation applications and to replace the existing non-standard technologies. It currently operates in the 868MHz band at a data rate of 20Kbps in Europe, 914MHz band at 40Kbps in the USA, and the 2.4GHz ISM bands Worldwide at a maximum data-rate of 250Kbps.

The ZIGBEE specification is a combination of Home RF Lite and the 802.15.4 specification. The specification operates in the 2.4GHz (ISM) radio band – the same band as 802.11b standard, Bluetooth, microwaves and some other devices. It is capable of connecting 255 devices per network. The specification supports data transmission rates of up to 250 Kbps at a range of up to 30 meters. ZIGBEE’s technology is slower than 802.11b (11 Mbps) and Bluetooth (1 Mbps) but it consumes significantly less power.

802.15.4 (ZIGBEE) is a new standard uniquely designed for low rate wireless personal area networks. It targets low data rate, low power consumption and low cost wireless networking, and its goal is to provide a physical-layer and MAC-layer standard for such networks.

Wireless networks provide advantages in deployment, cost, size and distributed intelligence when compared with wired networks. This technology allows users to set up a network quickly, and allows them to set up networks where it is impossible or inconvenient to wire cables. Wireless networks are more cost-efficient than wired networks in general.

Bluetooth (802.15.1) was the first well-known wireless standard facing low data rate applications. The effort of Bluetooth to cover more applications and provide quality of service has led to its deviation from the design goal of simplicity, which makes it expensive and inappropriate for some simple applications requiring low cost and low power consumption. These are the kind of applications this new standard is focused on. It’s relevant to compare here Bluetooth and ZIGBEE, as they are sometimes seen as competitors, to show their differences and to clarify for which applications suits each of them.

The data transfer capabilities are much higher in Bluetooth, which is capable of transmitting audio, graphics and pictures over small networks, and also appropriate for file transfers. ZIGBEE, on the other hand, is better suited for transmitting smaller packets over large networks; mostly static networks with many, infrequently used devices, like home automation, toys, remote controls, etc. While the performance of a Bluetooth network drops when more than 8 devices are present, ZIGBEE networks can handle 65000+ devices.

Probably the main feature of ZIGBEE is its limited power requirement. ZIGBEE is better for devices where the battery is rarely replaced, as it is designed to optimize slave power requirements, and battery life can be up to 2 years with normal batteries. Bluetooth is a cable replacement for items like phones, laptop computers and headsets. Bluetooth devices expect regular charging and use a power model like a mobile phone.

ZIGBEE is also outstanding when facing timing critical, low power applications. The join time for a new slave is typically 30ms, and the time needed by a slave changing from sleeping to active, or accessing the channel is typically 15ms. Bluetooth devices need 3 seconds to either join a network or to change to active from sleeping state, though they are much faster accessing the channel (around 2ms).

Need for ZIGBEE Technology:

ZIGBEE is the only wireless standards-based technology that addresses the unique needs of remote monitoring and control, sensory network applications. Sensors and controls don’t need high bandwidth but they do need low latency and very low energy consumption for long battery lives and for large device arrays.

There are a multitude of standards that address mid to high data rates for voice, PC LANs, video, etc.  However, up till now there hasn’t been a wireless network standard that meets the unique needs of sensors and control devices. There are a multitude of proprietary wireless systems manufactured today to solve a multitude of problems that also don’t require high data rates but do require low cost and very low current drain.

These proprietary systems were designed because there were no standards that met their requirements.  These legacy systems are creating significant interoperability problems with each other and with newer technologies.

This network has large number of nodes when compared to other technologies. It is easy to deploy and configure i.e., if any new node enters into the network it automatically senses and configure it. The Zigbee device is interoperable.

Features

 

• Standards-based wireless technology
• Interoperability and worldwide usability
• Low data-rates
• Ultra low power consumption
• Very small protocol stack
• Support for small to excessively large networks
• Simple design
• Security
• Reliability

Parameters

• Operating frequency  : 2.4GHz
• Operating voltage              : 3.3V
• Transmitted power   : 1mw
• Range     : 30m(urban area), 200m (LOS)
• Data rate    : 250Kbps
• Operating temperature range  : -40^oC to +80^oC
• Receiver sensitivity   : -104dbm
• Frequency range   : 2.4 – 2.4875 GHz.

Network Topologies

Fig 2.1 Network Topologies

There are three different network topologies that are supported by Zigbee, namely the star, mesh and cluster tree or hybrid networks. Each has its own advantages and can be used to advantage in different situations.

The star network is commonly used, having the advantage of simplicity.  In the star topology, the communication is established between devices and a single central controller, called the PAN coordinator. The PAN coordinator is the primary controller of the PAN. All devices operating on a network of either topology shall have unique 64 bit extended address, which can be exchanged for a short address allocated by the PAN coordinator when the device associates.

Mesh or peer-to-peer networks enable high degrees of reliability. The mesh topology also has a PAN coordinator, but any device can communicate with any other device as long as they are in range of one another. Mesh topology allows more complex network formations to be implemented. Mesh networking allows for redundancy in node links, so that if one node goes down, devices can find an alternative path to communicate with one another.

Cluster Tree network is essentially a combination of star and mesh topologies. Each independent PAN will select a unique identifier. This PAN identifier allows communications between devices within a network using short addresses and enables transmissions between devices across independent networks.

Network Elements

There are three network elements:

PAN Coordinator (Personal Area Network Coordinator)

• The central coordinator in a network is called PAN Coordinator.
• The PAN Coordinator is the primary controller of the PAN.
• Uses a specific 16-bit PAN ID.
• It has self healing property.

FFD (Full Function Device)

• This acts as a ZigBee Router.
• Helps form the mesh and route data.
• This performs other functions like sensing.

RFD (Reduced Function Device)

• This cannot act as a router.
• This is the end node of the network.
• One RFD node cannot communicate directly with other RFD node.

Wireless technologies

 

Fig 2.2 Various Wireless Technologies

The above figure illustrates data rates and operating range of Zigbee in comparison with other wireless technologies. The different technologies and standards mentioned above are classified under two networks.

• WPAN  (Wireless Personal Area Network)
• WLAN  (Wireless local Area Network)

In WPAN we have two competing technologies Zigbee, Bluetooth. The data rate of Zigbee is 250 kbps and that of Bluetooth is 1Mbps. Zigbee is focused on automation whereas Bluetooth focuses on connectivity between laptops and PDA’s.

In WLAN we have other technologies like WI-FI, WIMAX and HiperLAN. The data rates are high in WLAN which ranges from 1-54 Mbps. These technologies are costlier and complex when compared Zigbee. The below table shows the difference between different wireless technologies.

Table: 2.1 Comparisons of Various WLAN Technologies

	ZigBee	802.11  (Wi-Fi)	Bluetooth	UWB (Ultra Wide Band)	Wireless USB	IR Wireless
Data Rate	20, 40, and 250 Kbits/s	11 & 54 Mbits/sec	1 Mbits/s	100-500 Mbits/s	62.5 Kbits/s	20-40 Kbits/s
Range	10-100 meters	50-100 meters	10 meters	<10 meters	10 meters	<10 meters (LOS)
Networking Topology	peer to peer, star, or mesh	Point to hub	Ad-hoc, very small networks	Point to point	Point to point	Point to point
Operating Frequency	2.4 GHz	2.4 & 5 GHz	2.4 GHz	3.1-10.6 GHz	2.4 GHz	800-900 nm
Complexity	Low	High	High	Medium	Low	Low
Power Consumption	Very low	High	Medium	Low	Low	Low
Security	128 AES plus application layer security		64 and 128 bit encryption
Typical Applications	Industrial control and monitoring, sensor networks, building automation, home control	Wireless LAN connectivity, broadband Internet access	Wireless connectivity between devices such as phones, PDA, laptops, headsets	Streaming video, home entertainment applications	PC peripheral connections	Remote controls, PC, PDA, phone, laptop links

  Application:

 

• Building Automation

• HVAC Control
• Asset Tracking
• Building Lighting

• Industrial Control

• Asset Management
• Process Control
• Environmental Monitor
• Energy Management
• Metering

• Medical Sensing and Monitoring

• Patient monitoring
• Fitness monitoring

• Consumer Electronics
  • TV
  • VCR
  • DVD/CD
  • Remote Control
  • Interactive Toys
• BUILDING

• PC and Peripherals

• Mouse
• Keyboard
• Joystick

• Commercial control

• Home Security
• Lawn Irrigation
• Home Remote Control
• Home Remote monitor

ZIGBEE ARCHITECTURE

The IEEE 802.15.4 standard and Zigbee wireless network technology are ideal for the implementation of a wide range of low cost, low power and reliable control and monitoring applications within the private home and industrial environment. The working model of the IEEE 802.15.4 and Zigbee is illustrated in Figure 6.9.

Fig: 6.9 Zigbee Architecture

In the Zigbee architecture, the PHY layer and MAC layer are based on the IEEE 802.15.4 WPAN standard. Zigbee defines the NWK and APS layers. The software and hardware vendor will provide the software stack with appropriate tools to allow an OEM to create applications, which are added to the APL. The Physical (PHY) layer and Medium Access Control (MAC) layer are based on the IEEE802.15.4 PAN standard. This includes the actual radio hardware. Above the MAC and PHY are the Network (NWK) and application layers defined by Zigbee.

The first two layers, the physical (PHY) and Medium Access Control (MAC) are defined in the IEEE standard. The other layers that build on the PHY and MAC layers are defined by the Zigbee alliance.

The PHY layer contains the RF transceiver and access to the other hardware and control mechanisms. The function of the PHY is to activate and deactivate the radio transceiver and other hardware specific services such as access to the channels.

The MAC layer is as described by the name a controlling device for radio medium. It controls access to the physical radio channel and other services defined by the PHY service. It is also responsible for a reliable transmission system through its services. The services are about channel access and transmission techniques and validation of data packets.

The network (NWK) layer is responsible for the network controlling functions. It controls the mechanism for joining and leaving a network and for creating a network for those devices which have the capability to do so. The NWK layer applies also security to what is going to be data packets. The NWK layer is responsible for discovery and storing information about the neighbors in the network. Responsibility for routing between devices and routing of packets to their destination goes to this layer.

The application layer (APL) consists of three different blocks which have different functionalities and responsibilities. The application support sub-layer (APS) is responsible for maintaining a table of devices that are connected to each other, a binding table. The APS layer provides an interface between the NWK layer and the APL with its set of services.

The Zigbee device object (ZDO) is responsible for managing Zigbee devices in the network. This could be discovering new device in the network and define its role in the network it also determines the services the new device provides. Possible device types are those defined in Zigbee standard and they are coordinators, routers and end devices. The Application Frame (AF) contains application objects which can be manufacturer defined application objects. An example of an application object is a power switch.

The security service provider (SSP) provides enhanced security options as encryption with 128-bit key transport.

PHYSICAL LAYER

The physical layer is responsible for the radio hardware device. The standard defines two hardware Platforms for the IEEE 802.15.4. One describes the 2.4 GHz spectrum and one the 868/915 MHz spectrum.The lower band use different modulations technique and lower data rate. Explanations for the different bands are given in the regulations section. The lower band provides better radio performance when reviewing the frequency band and the antenna performance .specifications in the rest of the report apply only for the 2.4GHz band.

Frequency bands:

Table: 6.9 Operating Frequency Bands of Zigbee

PHY  (MHz)	Frequency  Band (MHz)	Spreading parameters		Data parameters
		Chip rate  (k chips/s)	Modulation	Bit rate  (kb/s)	Symbol rate  (k symbol/s)	symbols	channels
865/  915	868-868.6	300	BPSK	20	20	Binary	0
	902-928	600	BPSK	40	40	Binary	1-10
2400	2400-  2483.5	2000	O-QPSK	250	62.5	16-ary  Orthogonal	11-26

 

Responsibility

The layer is responsible for the hardware and can be divided into the following tasks:

• Activation and deactivation of radio transceiver.
• Data transmission and reception.
• Channel frequency selection.
• Indicator for radio quality within channels and for packets.
• Channel access assessment technique.

Layer service

 

The PHY data service is responsible of transport of MPDU between MAC peer sub-layers through the PD-SAP. This is done by data primitives such as PD-DATA request. The PLME is responsible for managing a database of managed objects by the PHY. It is referred to as PHY information base (PIB). The PLME-SAP is responsible for management commands between the MAC layer management entity (MLME) and the PLME. The primitives that are provided are defined for the PLME. They provide for example performing CCA, Energy Detection (ED) measurements or accessing the PIB data base.

PHY enumeration descriptions, constants and PIB attributes are defined in a table in the standard. The maximum PSDU that the PHY shall be able to receive from the MAC layer is 127 octets as described in the introduction. Turnaround times for TX-to-RX and RX-to-TX shall be a maximum of 12 data symbol periods. Each symbol is 4 bits which gives a maximum turnaround time of 6 octet periods.

The spreading of the data decreases the raw data transfer but leads to a much higher reliability in the transmission. Errors in the baseband chip sequence do not mean errors in the raw data. The probability to recognize the correct symbol even if bit errors have occurred is high. The O-QPSK modulation used is equivalent to MSK modulation. It utilizes constant amplitude and enables use of relatively nonlinear amplifier designs which means more simple and low cost construction.

MAC LAYER

The MAC layer is responsible for accessing the physical radio channel through the PHY layer. It provides services to enable reliable single –hop communication links between devices in a network. The services are about channel access and transmission techniques and validation of data packets.

Layer Service

The services provided by the MAC layer can be divided into these sub groups:

• Providing a single-hop peer link between MAC entities.
• Supporting PAN association and dissociation.
• Using CSMA-CA mechanism for channel access.
• Handling and maintaining of GTS mechanism.
• Generate network beacons if device is coordinator.
• Synchronization to network beacons.
• Supporting device security.

Layer Structure

The structure communication model is similar to the PHY layer. The MAC layer includes a management entity (MLME) which provides interface to management entities on other devices. The MLME is also responsible of maintaining a data base of management objects. The MAC sub-layer provides two services accessed through the data entity and management. The services are provided for the PHY layer and next higher layer. Data services provided by the MAC layer are those for requesting and confirming data for example. Management services in the MAC layer is among others association primitives, beacon primitives and channel scanning primitives.

CSMA-CA  

The CSMA-CA algorithm implements time units called backoff periods. In slotted CSMA-CA the backoff periods of every device in the network are aligned with the super frame boundaries of the coordinator. In the unslotted CSMA-CA the backoff periods of devices in the network are not related in time to any other device 9in the PAN.

The IEEE 802.15.4 MAC sub layer controls the access to the radio channel using the CSMA-CA (Carrier Sense Multiple Access with Collision Avoidance) method, and handles network (dis)association and MAC layer security (AES-128 encryption based). It is also responsible for flow control via acknowledgement and retransmission of data packets, frame validation, and network synchronization as well as support to upper layers for robust link operation. The Zigbee wireless technology specifies the network, security, and application layers upon the IEEE 802.15.4 PHY and MAC layers. The Zigbee Alliance also provides interoperability and conformance testing specifications.

Channel Access

There are two types of channel access in the IEEE 802.15.4 defined communication system. They are based on contention which decides if the devices retain their own time slot for communication. The contention based allows the devices to access channel in the distributed way using CSMA-CA algorithm. With this contention free method the network coordinator decides about the channel access with the use of Guaranteed Time Slots (GTS) of the channel space. This contention free method is suitable for latency sensitive devices that require short delay time and no competition of the channel access.

Transmission

Transmission, reception and acknowledgements are procedures for sending data, receiving data and for acknowledging that data has been received or sent. Retransmission of data if error occurs if bounded to acknowledgments procedures that are optional.

Security

The MAC layer is responsible for providing security services when requested by higher layers. The higher layers are responsible for information necessary to provide needed security services. Key management, device authentication and freshness protection may be services provided by higher layers but out of the scope for this standard..

The IEEE 802.15.4 supports the following security services:

• Access control
• Data encryption
• Frame integrity
• Sequential freshness

The security can be implemented on both incoming and outgoing frames.

Access control provides and maintains an Access Control List (ACL). The list contains devices that have been selected and approved for communicating with. Data encryption security service uses a symmetric cipher to encrypt data for parties who do not have the cryptographic key. In this standard the data encryption may be provided on beacon payloads, command payloads and data payloads. Frame integrity service provides assurance that data have not been modified by parties without the cryptographic key and also that data originates from sources with the key. The service may be provided on beacon frames, command frames and data frames. Sequential freshness uses a sequence to protect from frames that are not the original in some manner.

NETWORK LAYER

 

The NWK layer is the first Zigbee layer. It is build upon the MAC and PHY layers. The NWK layer provides services for routing and multi-hop communication needed to build different network topologies it is required for correct functionality for underlying layers. It acts as a interface for next higher layer, the application layer. It includes a NWK layer management entity (NLME). The NLME and the NWK layer data entity (NLDE) uses the NLME-SAP and the NLDE-SAP for communicating to other layers.

The NLDE provides two kinds of services

• Generate NWK Protocol Data Unit (NPDU) from next higher layer, APS layer.
• Deliver NPDU to recipient or route it to the next step towards the destination.

The NLME provides the following services:

• Configuring a new device
• Starting a network
• Joining and leaving a network
• Addressing
• Neighbour discovery
• Route discovery
• Reception control

Attributes

 

A list of constants is characterizing the NWK layer. A list of attributes is also given and it is used to manage the NWK layer of a device. An attribute is a data entity that represents a physical quantity or a state. The attribute data is sent using commands.

 

Building network

 

The procedures for building networks are build on those defined in the MAC layer. Only coordinators are able to build a network. After that is guaranteed an ED scan is performed followed by an active scan. When data is processed a PAN identifier is selected, channel selction are made and a network address is assigned.

Joining network

Coordinators and routers can permit devices to join the network. The relationship between the device that provides permission and the device that wants to join the network is called a parent-child relationship. A parent can directly accept a child and join it to the network with the 64 bit IEEE address. The child retains then a short logical address. When a device wants to join a network first a scan procedure is performed. A suitable parent is searched for from the neighbour table. Joining the network is then done by an association request. If joining was successful the new device receives a 16 bit short address for communication within the network. The devices are then updating the information in their neighbour tables. Orphaning is the procedure that is performed when a child loose connection to its network or to its parent.

The leaving of a network can be done either by request from the child or as a request from the parent to force the child device to leave the network. Every device has an associated depth. It tells the minimum hops a data frame has to perform through parent links to reach the coordinator. The coordinator itself has 0 depth and its children have 1 depth. The maximum depth of the network is decided by the coordinator. Neighbour tables shall contain information about devices within a specified transmission range. The information shall be used for different purpose and contains basic device and network information. It can also be increased with more information. A table entry shall be updated each time a device receives a frame from the neighbor. The addressing of joined devices can be assigned in two ways. Either as distributed address assignment mechanism or as higher-layer address assignment mechanism.

APL LAYER

The application layer is the second of two Zigbee layers. The application layer houses the responsibility for overall device management. It is also responsible for applications and service function within the application layer and to the NWK layer. The application layer consists of the APS, AF and ZDO.

There are two addressing concepts for Zigbee devices. It consists of addressing the specific radio hardware or the application object. They are called node addressing respective endpoint addressing. A node refers to a single radio device. A node could consist of several subunits where each subunit has a device description. Each subunit is assigned its own specific endpoint which range from 1 to 240. Each endpoint has a description that describes for example what it does and which attributes it has. Attributes are variables that represent physical quantity or states. In a typical application an attribute could be temperature and endpoints could be sensor applications for temperature and humidity. A cluster is identifier of messages that are sent and are also container for attributes. A Zigbee device would then represent a node that could be an indoors climate report station and another Zigbee device node a controller and communication central for a climate control centre.

Application support sub-layer (APS)

 

The APS provides interface between the NWK layer and application layer. The services are offered via the two services, APS Data Entity (APSDE) and APS Management Entity (APSME). The APSDE provides data transmission through its APSDE-SAP and the management entity provides all other services through APSME-SAP.

The APSDE provides these services

• Generation of APDU-APS layer specific frame are generated
• Binding-Transmission between matched devices

The APSME provides these services:

• Interaction with Zigbee Stack
• Binding-Ability to match devices
• Security-Security relationships with use of keys

Transmission

If an indirect transmission is sent the originating device shall direct the transmission to the Zigbee coordinator which handles message reflection. The Zigbee coordinator contains the binding table and shall search for table entry that matches the source address, the cluster identifier or the source endpoint field. The transmission shall be directed to each of these matched entries. The source address is retained from the NWK layer, the cluster identifier and the source endpoint is included in the frame. The indirect transmission shall include the source endpoint or destination endpoint field depending on direction with respect to the coordinator. If the transmission is towards the coordinator for relay it shall contain destination endpoint. If it is directed from coordinator after relay it shall contain the source endpoint. Acknowledgement is optional and in indirect addressing the coordinator shall answer acknowledgement request from originating devices and requesting acknowledgement from devices that frames are relayed to. Retransmissions are bound to acknowledgement. When acknowledge is enabled retransmission shall be performed if error occurs.

Application Framework (AF)

The application frame work is containing the application objects and provides services that the application uses. The applications communicate through the APSDE-SAP. The control and management of application frame is performed by ZDO public interfaces. The primitives is as for the APS sub-layer request, confirm and indication.

Endpoints

 

The application framework can house up to 240 application objects. Each one is defined on an endpoint with index from 1 to 240, see figure 2.13. Endpoint 0 is reserved and is used for interface to the ZDO and endpoint 255 is reserved for broadcasting of data to all application objects.

ZDO 

The ZDO is responsible for overall device management and handling of services. It uses its services to implement three different logical Zigbee devices, coordinator, router and end device. The ZDO is interfacing the management entities of the NWK and the APS sub-layer.

The ZDO is responsible for assembling data configuration from end points to implement these functions:

• Device and service discovery
• Security manager
• Network manager
• Node manager

 

ZIGBEE TRANSCEIVER

Pin Diagram

 

Fig: 6.1 Pin diagram of X-Bee Transceiver

Zigbee modules feature a UART interface, which allows any microcontroller or microprocessor to immediately use the services of the Zigbee protocol. All a Zigbee hardware designer has to do in this ase is ensure that the host’s serial port logic levels are compatible with the XBee’s 2.8- to 3.4-V logic levels. The logic level conversion can be performed using either a standard RS-232 IC or logic level translators such as the 74LVTH125 when the host is directly connected to the XBee UART. The below table gives the pin description of transceiver.

Table: 6.1 Pin Description of X-Bee Transceiver

Pin	Name	Direction	Description
1	Vcc	–	Power Supply
2	DOUT	Output	UART Data Out
3	DIN/CONFIG	Input	UART Data In
4	DO8	Output	Digital Output 8
5	RESET	Input	Module Reset
6	PWM0/RSSI	Output	PWM Output 0/RX Signal Strength Indicator
7	PWM1	Output	PWM Output 1
8	[reserved]	–	Do not connect
9	DDR/SLEEP_RQ/DI8	Input	Pin Sleep Control Line or Digital Input 8
10	GND	–	Ground
11	AD4/DIO4	Either	Analog Input 4 or Digital I/O 4
12	CTS/DIO7	Either	Clear-to-Send Flow Control or Digital I/O 7
13	ON/SLEEP	Output	Module Status Indicator
14	VREF	Input	Voltage Reference for A/D Inputs
15	Associate/AD5/DIO5	Either	Associated Indicator, Analog Input 5 or Digital I/O 5
16	RTS/AD6/DIO6	Either	Request-to-Send Flow Control, Analog Input 6 or Digital I/O 6
17	AD3/DIO3	Either	Analog Input 3 or Digital I/O 3
18	AD2/DIO2	Either	Analog Input 2 or Digital I/O 2
19	AD1/DIO1	Either	Analog Input 1 or Digital I/O 1
20	AD0/DIO0	Either	Analog Input 0 or Digital I/O 0

Design Notes:

• Minimum connections: VCC, GND, DOUT & DIN
• Minimum connections for updating firmware: VCC, GND, DIN, DOUT, RTS and DTR
• Signal Direction is specified with respect to the module
• Module includes a 50k pull-up resistor attached to RESET
• Several of the input pull-ups can be configured using the PR command
• Unused pins should be left disconnected

Features:

Performance:

Table: 6.2 Performance characteristics

Parameters	Value
Indoor/Urban Range	30m
Outdoor RF (LOS)	100m
Transmit Power Output	1mW (0dBm)
RF Data Rate	250,000bps
Serial Interface Data Rate	1200-115200bps
Receiver Sensitivity	-92dBm

Power Requirements:

Table: 6.3 Power Requirement characteristics

Parameters	Value
Supply Voltage	2.8 – 3.4V
Transmit Current	45mA
Receive Current	50mA

General:

Table: 6.4 General characteristics

Parameters	Value
Operating Frequency	ISM 2.4GHz
Dimensions	2.468 x 2.761
Operating Temperature	-40o to 85o C
Antenna Options	Integrated Chip Antenna

Networking and Security:

Table: 6.5 Networking and Security characteristics

Parameters	Value
Supported Network Topologies	Point­-to-point, Point-to-multipoint, Peer-to-peer
Number of Channels	16 Direct Sequence Channels
Addressing Options	PAN ID, Channel and Addresses

6.3 System Data Flow Diagram

Fig: 6.2 Data Flow Diagram

The X-Bee RF Modules interface to a host device through a logic-level asynchronous

Serial port. Through its serial port, the module can communicate with any logic and voltage

Compatible UART; or through a level translator to any serial device.

Data is presented to the X-Bee module through its DIN pin, and it must be in the asynchronous serial format, which consists of a start bit, 8 data bits, and a stop bit. Because the input data goes directly into the input of a UART within the X-Bee module, no bit inversions are necessary within the asynchronous serial data stream. All of the required timing and parity checking is automatically taken care of by the X-Bee’s UART.

Just in case you are producing data faster than the X-Bee can process and transmit it, both X-Bee modules incorporate a clear-to-send (CTS) function to throttle the data being presented to the X-Bee module’s DIN pin. You can eliminate the need for the CTS signal by sending small data packets at slower data rates.

If the microcontroller wants to send data to transceiver, it will send RTS (Request to Send) signal. If the transceiver is idle it sends CTS (Clear to Send) signal. The RTS and CTS signals are active low. When microcontroller receives CTS command it will send data to the transceiver through DIN pin. The transceiver will send the data to microcontroller through DOUT pin. The communication between transceiver and the microcontroller at the transmitter and receiver is similar. The communication between transmitter and receiver is through RF communication.

6.4 Serial Data

         

Fig: 6.3 Serial Data Sequence

For example:

UART data packet 0x1F (decimal number is 31) as transmitted through the RF module.

Data enters the module UART through the DI pin (pin 3) as an asynchronous serial signal. The signal should idle high when no data is being transmitted. Each data byte consists of a start bit (low), 8 data bits (least significant bit first) and a stop bit (high). The following figure illustrates the serial bit pattern of data passing through the module.

 

The module UART performs tasks, such as timing and parity checking, that are needed for data communications. Serial communications depend on the two UARTs to be configured with compatible settings (baud rate, parity, start bits, stop bits, data bits).

X-Bee RF Modules operate in Transparent Mode. When operating in this mode, the modules act as a serial line replacement – all UART data received through the DI pin is queued up for RF transmission. When RF data is received, the data is sent out the DO pin.

Serial-to-RF Packetization

Data is buffered in the DI buffer until one of the following causes the data to be packetized and transmitted:

• No serial characters are received for the amount of time determined by the RO (Packetization Timeout) parameter. If RO = 0, packetization begins when a character is received.
• The maximum number of characters that will fit in an RF packet (100) is received.
• The Command Mode Sequence (GT + CC + GT) is received. Any character buffered in the DI buffer before the sequence is transmitted.

If the module cannot immediately transmit (for instance, if it is already receiving RF data), the serial data is stored in the DI Buffer. The data is packetized and sent at any RO timeout or when 100 bytes (maximum packet size) are received.

If the DI buffer becomes full, hardware or software flow control must be implemented in order to prevent overflow (loss of data between the host and module).

6.5 Internal Data Flow

    

Fig: 6.4 Internal Data Flow Diagram

DI (Data In) Buffer:

When serial data enters the RF module through the DI pin (pin 3), the data is stored in the DI Buffer until it can be processed.

Hardware Flow Control (CTS):

When the DI buffer is 17 bytes away from being full; by default, the module de-asserts CTS (high) to signal to the host device to stop sending data [refer to D7 (DIO7 Configuration) parameter]. CTS are re-asserted after the DI Buffer has 34 bytes of memory available.

How to eliminate the need for flow control:

• Send messages that are smaller than the DI buffer size.
• Interface at a lower baud rate [BD (Interface Data Rate) parameter] than the throughput data rate.

 

Case in which the DI Buffer may become full and possibly overflow:

If the module is receiving a continuous stream of RF data, any serial data that arrives on the DI pin is placed in the DI Buffer. The data in the DI buffer will be transmitted over-the-air when the module is no longer receiving RF data in the network.

DO (Data Out) Buffer:

When RF data is received, the data enters the DO buffer and is sent out the serial port to a host device. Once the DO Buffer reaches capacity, any additional incoming RF data is lost.

Hardware Flow Control (RTS):

If RTS is enabled for flow control (D6 (DIO6 Configuration) Parameter = 1), data will not be sent out the DO Buffer as long as RTS (pin 16) is de-asserted.

Two cases in which the DO Buffer may become full and possibly overflow:

• If the RF data rate is set higher than the interface data rate of the module, the module will receive data from the transmitting module faster than it can send the data to the host.
• If the host does not allow the module to transmit data out from the DO buffer because of being held off by hardware or software flow control.

6.6     I/O Data Format

I/O data begins with a header. The first byte of the header defines the number of samples forthcoming. A sample is comprised of input data and the inputs can contain either DIO or ADC. The last 2 bytes of the header (Channel Indicator) define which inputs are active. Each bit represents either a DIO line or ADC channel.

Fig: 6.5 Header of I/O Data Format

Sample data follows the header and the channel indicator frame is used to determine how to read the sample data. If any of the DIO lines are enabled, the first 2 bytes are the DIO data and the ADC data follows. ADC channel data is stored as an unsigned 10-bit value right-justified on a 16-bit boundary.

Sample Data

Fig: 6.6 Sample Data of I/O Data Format

6.7 Networks:

The following IEEE 802.15.4 network types are supported by the Zigbee RF modules:

• NonBeacon

• NonBeacon (w/ Coordinator)

The following terms will be used to explicate the network operations:

Table 6.6: Terms and definitions:

Term	Definition
PAN	Personal Area Network – A data communication network that includes one or more End Devices and optionally a Coordinator.
Coordinator	A Full-function device (FFD) that provides network synchronization by polling nodes [NonBeacon (w/ Coordinator) networks only]
End Device	When in the same network as a Coordinator – RF modules that rely on a Coordinator for synchronization and can be put into states of sleep for low-power applications.
Association	The establishment of membership between End Devices and a Coordinator. Association is only applicable in NonBeacon (w/Coordinator) networks.

6.7.1NonBeacon:

By default, XBee/XBee-PRO RF Modules are configured to support NonBeacon communications. NonBeacon systems operate within a Peer-to-Peer network topology and therefore are not depen-dent upon Master/Slave relationships. This means that modules remain synchronized without use of master/server configurations and each module in the network shares both roles of master and slave. MaxStream’s peer-to-peer architecture features fast synchronization times and fast cold start times. This default configuration accommodates a wide range of RF data applications.

A peer-to-peer network can be established by configuring each module to operate as an End Device (CE = 0), disabling End Device Association on all modules (A1 = 0) and setting ID and CH parameters to be identical across the network.

Figure 6.7: NonBeacon Peer-to-Peer Architecture

6.7.2 NonBeacon (w/ Coordinator):

A device is configured as a Coordinator by setting the CE (Coordinator Enable) parameter to “1”. Coordinator power-up is governed by the A2 (Coordinator Association) parameter.

In a NonBeacon (w/ Coordinator) system, the Coordinator can be configured to use direct or indi-rect transmissions. If the SP (Cyclic Sleep Period) parameter is set to “0”, the Coordinator will send data immediately. Otherwise, the SP parameter determines the length of time the Coordinator will retain the data before discarding it. Generally, SP (Cyclic Sleep Period) and ST (Time before Sleep) parameters should be set to match the SP and ST settings of the End Devices.

6.7.3 Association:

Association is the establishment of membership between End Devices and a Coordinator and is only applicable in NonBeacon (w/ Coordinator) networks. The establishment of membership is useful in scenarios that require a central unit (Coordinator) to relay messages to or gather data from several remote units (End Devices), assign channels or assign PAN IDs.

An RF data network that consists of one Coordinator and one or more End Devices forms a PAN (Personal Area Network). Each device in a PAN has a PAN Identifier [ID (PAN ID) parameter]. PAN IDs must be unique to prevent miscommunication between PANs. The Coordinator PAN ID is set using the ID (PAN ID) and A2 (Coordinator Association) commands.

An End Device can associate to a Coordinator without knowing the address, PAN ID or channel of the Coordinator. The A1 (End Device Association) parameter bit fields determine the flexibility of an End Device during association. The A1 parameter can be used for an End Device to dynamically set its destination address, PAN ID and/or channel.

 

Coordinator / End Device Setup and Operation

To configure a module to operate as a Coordinator, set the CE (Coordinator Enable) parameter to ‘1’. Set the CE parameter of End Devices to ‘0’ (default). Coordinator and End Devices should con-tain matching firmware versions.

NonBeacon (w/ Coordinator) Systems

In a NonBeacon (w/ Coordinator) system, the Coordinator can be configured to use direct or indirect transmissions. If the SP (Cyclic Sleep Period) parameter is set to ‘0’, the Coordinator will send data immediately. Otherwise, the SP parameter determines the length of time the Coordinator will retain the data before discarding it. Generally, SP (Cyclic Sleep Period) and ST (Time before Sleep) parameters should be set to match the SP and ST settings of the End Devices.

Coordinator Power-up

Coordinator power-up is governed by the A2 (Coordinator Association) command. On power-up, the Coordinator undergoes the following sequence of events:

1. Check A2 parameter- Reassign_PANID Flag:

Set (bit 0 = 1) – The Coordinator issues an Active Scan. The Active Scan selects one channel and transmits a Beacon Request command to the broadcast address (0xFFFF) and broadcast PAN ID (0xFFFF). It then listens on that channel for beacons from any Coordinator operating on that channel. The listen time on each channel is determined by the SD (Scan Duration) parameter value.

Once the time expires on that channel, the Active Scan selects another channel and again transmits the BeaconRequest as before. This process continues until all channels have been scanned, or until 5 PANs have been discovered. When the Active Scan is complete, the results include a list of PAN IDs and Channels that are being used by other PANs. This list is used to assign an unique PAN ID to the new Coordinator. The ID parameter will be retained if it is not found in the Active Scan results. Otherwise, the ID (PAN ID) parameter setting will be updated to a PAN ID that was not detected.

Not Set (bit 0 = 0) – The Coordinator retains its ID setting. No Active Scan is performed. For example: If the PAN ID of a Coordinator is known, but the operating channel is not; the A1 command on the End Device should be set to enable the ‘Auto_Associate’ and ‘Reassign Channel’ bits. Additionally, the ID parameter should be set to match the PAN ID of the associated Coordinator.

 

 

2. Check A2 parameter – Reassign Channel Flag (bit 1)

Set (bit 1 = 1) – The Coordinator issues an Energy Scan. The Energy Scan selects one channel and scans for energy on that channel. The duration of the scan is specified by the SD (Scan Duration) parameter. Once the scan is completed on a channel, the Energy Scan selects the next channel and begins a new scan on that channel. This process continues until all channels have been scanned.

When the Energy Scan is complete, the results include the maximal energy values detected on each channel. This list is used to determine a channel where the least energy was detected. If an Active Scan was performed (Reassign_PANID Flag set), the channels used by the detected PANs are eliminated as possible channels. Thus, the results of the Energy Scan and the Active Scan (if performed) are used to find the best channel (channel with the least energy that is not used by any detected PAN). Once the best channel has been selected, the CH (Channel) param-eter value is updated to that channel.

Not Set (bit 1 = 0) – The Coordinator retains its CH setting. An Energy Scan is not performed.

3. Start Coordinator

The Coordinator starts on the specified channel (CH parameter) and PAN ID (ID parameter). Note, these may be selected in steps 1 and/or 2 above. The Coordinator will only allow End Devices to associate to it if the A2 parameter “Allow Association” flag is set. Once the Coordinator has successfully started, the Associate LED will blink 1 time per second. (The LED is solid if the Coordinator has not started.)

4. Coordinator Modifications

Once a Coordinator has started:

Modifying the A2 (Reassign_Channel or Reassign_PANID bits), ID, CH or MY parameters will cause the Coordinator’s MAC to reset (The Coordinator RF module (including volatile RAM) is not reset). Changing the A2 AllowAssociation bit will not reset the Coordinator’s MAC. In a non-beaconing system, End Devices that associated to the Coordinator prior to a MAC reset will have knowledge of the new settings on the Coordinator. Thus, if the Coordinator were to change its ID, CH or MY settings, the End Devices would no longer be able to communicate with the non-beacon Coordinator. Once a Coordinator has started, the ID, CH, MY or A2 (Reassign_Channel or Reassign_PANID bits) should not be changed.

End Device Power-up

End Device power-up is governed by the A1 (End Device Association) command. On power-up, the End Device undergoes the following sequence of events:

1. Check A1 parameter – AutoAssociate Bit

Set (bit 2 = 1) – End Device will attempt to associate to a Coordinator.

Not Set (bit 2 = 0) – End Device will not attempt to associate to a Coordinator. The End Device will operate as specified by its ID, CH and MY parameters. Association is considered complete and the Associate LED will blink quickly (5 times per second). When the AutoAssociate bit is not set, the remaining steps (2-3) do not apply.

2. Discover Coordinator (if Auto-Associate Bit Set)

The End Device issues an Active Scan. The Active Scan selects one channel and transmits a BeaconRequest command to the broadcast address (0xFFFF) and broadcast PAN ID (0xFFFF). It then listens on that channel for beacons from any Coordinator operating on that channel. The listen time on each channel is determined by the SD parameter.

Once the time expires on that channel, the Active Scan selects another channel and again transmits the BeaconRequest command as before. This process continues until all channels have been scanned, or until 5 PANs have been discovered. When the Active Scan is complete, the results include a list of PAN IDs and Channels that are being used by detected PANs.

The End Device selects a Coordinator to associate with according to the A1 parameter “Reassign_PANID” and “Reassign_Channel” flags:

Reassign_PANID Bit Set (bit 0 = 1)– End Device can associate with a PAN with any ID value.

Reassign_PANID Bit Not Set (bit 0 = 0) – End Device will only associate with a PAN whose ID setting matches the ID setting of the End Device.

Reassign_Channel Bit Set (bit 1 = 1) – End Device can associate with a PAN with any CH value.

Reassign_Channel Bit Not Set (bit 1 = 0)– End Device will only associate with a PAN whose CH setting matches the CH setting of the End Device.

After applying these filters to the discovered Coordinators, if multiple candidate PANs exist, the End Device will select the PAN whose transmission link quality is the strongest. If no valid Coordinator is found, the End Device will either go to sleep (as dictated by its SM (Sleep Mode) parameter) or retry Association.

Note – An End Device will also disqualify Coordinators if they are not allowing association (A2 – AllowAssociation bit); or, if the Coordinator is not using the same NonBeacon scheme as the End Device. (They must both be programmed with NonBeacon code.)

3. Associate to Valid Coordinator

Once a valid Coordinator is found (step 2), the End Device sends an Association Request message to the Coordinator. It then waits for an Association Confirmation to be sent from the Coordinator. Once the Confirmation is received, the End Device is Associated and the Associate LED will blink rapidly (2 times per second). The LED is solid if the End Device has not associated.

4. End Device Changes once an End Device has associated

Changing A1, ID or CH parameters will cause the End Device to disassociate and restart the Association procedure.

If the End Device fails to associate, the AI command can give some indication of the failure.

6.8 Zigbee Addressing:

Every RF data packet sent over-the-air contains a Source Address and Destination Address field in its header. The RF module conforms to the 802.15.4 specification and supports both short 16-bit addresses and long 64-bit addresses. A unique 64-bit IEEE source address is assigned at the factory and can be read with the SL (Serial Number Low) and SH (Serial Number High) commands. Short addressing must be configured manually. A module will use its unique 64-bit address as its Source Address if its MY (16-bit Source Address) value is “0xFFFF” or “0xFFFE”. To send a packet to a specific module using 64-bit addressing: Set Destination Address (DL + DH) to match the Source Address (SL + SH) of the intended destination module. To send a packet to a specific module using 16-bit addressing: Set DL (Destination Address Low) parameter to equal the MY parameter and set the DH (Destination Address High) parameter to ‘0’.

6.8.1 Unicast Mode

By default, the RF module operates in Unicast Mode. Unicast Mode is the only mode that supports retries. While in this mode, receiving modules send an ACK (acknowledgement) of RF packet reception to the transmitter. If the transmitting module does not receive the ACK, it will re-send the packet up to three times or until the ACK is received.

Short 16-bit addresses.

The module can be configured to use short 16-bit addresses as the Source Address by setting (MY < 0xFFFE). Setting the DH parameter (DH = 0) will configure the Destination Address to be a short 16-bit address (if DL < 0xFFFE). For two modules to communicate using short addressing, the Destination Address of the transmitter module must match the MY parameter of the receiver. The following table shows a sample network configuration that would enable Unicast Mode communications using short 16-bit addresses.

Table 6.7:Unicast Network Configuration (using 16-bit addressing)

Parameter	RF Module 1	RF Module 2
MY(source address)	0x01	0x02
DH(Destination High)	0	0
DL(Destination Low)	0x02	0x01

Long 64-bit addresses:

The RF module’s serial number (SL parameter concatenated to the SH parameter) can be used as a 64-bit source address when the MY (16-bit Source Address) parame-ter is disabled. When the MY parameter is disabled (set MY = 0xFFFF or 0xFFFE), the module’s source address is set to the 64-bit IEEE address stored in the SH and SL parameters. When an End Device associates to a Coordinator, its MY parameter is set to 0xFFFE to enable 64- bit addressing. The 64-bit address of the module is stored as SH and SL parameters. To send a packet to a specific module, the Destination Address (DL + DH) on one module must match the Source Address (SL + SH) of the other.

6.8.2 Broadcast Mode:

Any RF module within range will accept a packet that contains a broadcast address. When configured to operate in Broadcast Mode, receiving modules do not send ACKs (Acknowledgements) and transmitting modules do not automatically re-send packets as is the case in Unicast Mode. To send a broadcast packet to all modules regardless of 16-bit or 64-bit addressing, set the destination addresses of all the modules as shown below.

Sample Network Configuration (All modules in the network):

• DL (Destination Low Address) = 0x0000FFFF

• DH (Destination High Address) = 0x00000000 (default value)

 

6.8Modes of Operation

The Transceiver operates in five modes .They are

1. Idle Mode

2. Receive mode

3. Transmit Mode

4. Sleep Mode

5. Command Mode     

              

Fig: 6.7DifferentModes of Operation

The operation of Transceiver in each mode is explained below

1. Idle mode

When not receiving or transmitting data, the RF module is in Idle Mode. The module shifts into the other modes of operation under the following conditions:

• Transmit Mode (Serial data is received in the DI Buffer)
• Receive Mode (Valid RF data is received through the antenna)
• Sleep Mode (Sleep Mode condition is met)
• Command Mode (Command Mode Sequence is issued)

Transmit Mode

 RF data packets:

 

When not receiving or transmitting data, the RF module is in Idle Mode. The module shifts into the each transmitted data packet contains a Source Address and Destination Address field. The Source Address matches the address of the transmitting module as specified by the MY (Source Address) parameter (if MY >= 0xFFFE), the SH (Serial Number High) parameter or the SL (Serial Number Low) parameter. The <Destination Address> field is created from the DH (Destination Address High) and DL (Destination Address Low) parameter values. The Source Address and/or Destination Address fields will either contain a 16-bit short or long 64-bit long address.

There are two methods to transmit data. They are

 

1. Direct Transmission

If the source address matches the destination address then Data is transmitted immediately to the Destination Address. A NonBeaconing Coordinator can be configured to use only Direct Transmission by setting the SP (Cyclic Sleep Period) parameter to “0”. Also, a NonBeaconing Coordinator using indirect transmissions will revert to direct transmission if it knows the destination module is awake. To enable this behavior, the ST (Time before Sleep) value of the Coordinator must be set to match the ST value of the End Device. Once the End Device either transmits data to the Coordinator or polls the Coordinator for data, the Coordinator will use direct transmission for all subsequent data transmissions to that module address until ST time (or number of beacons) occurs with no activity (at which point it will revert to using indirect transmissions for that module address). “No activity” means no transmission or reception of messages with a specific address. Global messages will not reset the ST timer.

2. Indirect Transmission

 

A packet is retained for a period of time and is only transmitted after the destination module (Source Address = Destination Address) requests the data. To configure Indirect Transmissions in a PAN (Personal Area Network), the SP (Cyclic Sleep Period) parameter value on the Coordinator must be set to match the longest sleep value of any End Device. The SP parameter represents time in NonBeacon systems and beacons in Beacon-enabled systems. The sleep period value on the Coordinator determines how long (time or number of beacons) the Coordinator will retain an indirect message before discarding it. In NonBeacon networks, an End Device must poll the Coordinator once it wakes from Sleep to determine if the Coordinator has an indirect message for it. For Cyclic Sleep Modes, this is done automatically every time the module wakes (after SP time). For Pin Sleep Modes, the A1 (End Device Association) parameter value must be set to enable Coordinator polling on pin wake-up. Alternatively, an End Device can use the FP (Force Poll) command to poll the Coordinator as needed.

Indirect Transmissions can only occur on a Coordinator. Thus, if all nodes in a network are End Devices, only Direct Transmissions will occur. Indirect Transmissions are useful to ensure packet delivery to a sleeping node. The Coordinator currently is able to retain up to 2 indirect messages.

CCA (Clear Channel Assessment)

 

Prior to transmitting a packet, a CCA (Clear Channel Assessment) is performed on the channel to determine if the channel is available for transmission. The detected energy on the channel is compared with the CA (Clear Channel Assessment) parameter value. If the detected energy exceeds the CA parameter value, the packet is not transmitted. Also, a delay is inserted before a transmission takes place. This delay is settable using the RN (Back off Exponent) parameter. If RN is set to “0”, then there is no delay before the first CCA is performed. The RN parameter value is the equivalent of the “minBE” parameter in the 802.15.4 specification. The transmit sequence follows the 802.15.4 specification. By default, the MM (MAC Mode) parameter = 0. On a CCA failure, the module will attempt to resend the packet up to two additional times. When in Unicast packets with RR (Retries) = 0, the module will execute two CCA retires. Broadcast packets always get two CCA retires.

Acknowledgement

 

If the transmission is not a broadcast message, the module will expect to receive an acknowledgement from the destination node. If an acknowledgement is not received, the packet will be resent up to 3 more times. If the acknowledgement is not received after all transmissions, an ACK failure is recorded.

 

Sleep Mode

 

Sleep Modes enable the RF module to enter states of low-power consumption when not in use. In order to enter Sleep Mode, one of the following conditions must be met (in addition to the module having a non-zero SM parameter value):

• Sleep_RQ (pin 9) is asserted.
• The module is idle (no data transmission or reception) for the amount of time defined by the ST (Time before Sleep) parameter. (ST is only active when SM = 4-5).

The SM command is central to setting Sleep Mode configurations. By default, Sleep Modes are disabled (SM = 0) and the module remains in Idle/Receive Mode. When in this state, the module is constantly ready to respond to serial or RF activity.

Higher Voltages

 

 Sleep Mode current consumption is highly sensitive to voltage. Voltages above 3.0V will cause much higher current consumption.

Command mode

 

To modify or read RF Module parameters, the module must first enter into Command Mode – a state in which incoming characters are interpreted as commands. Two Command Mode options are supported: AT Command Mode and API Command Mode.

6.8 AT Command Mode

 

  To Enter AT Command Mode:

 

Send the 3-character command sequence “+++” and observe guard times before and after the command characters.

AT Command Mode Sequence (for transition to Command Mode):

• No characters sent for one second [GT (Guard Times) parameter = 0x3E8].
• Input three plus characters (“+++”) within one second [CC (Command Sequence Character) Parameter = 0x2B].
• No characters sent for one second [GT (Guard Times) parameter = 0x3E8].

All of the parameter values in the sequence can be modified to reflect user preferences.

To Send AT Commands:

 

             

Fig: 6.8 Syntax for sending AT Commands

The preceding example would change the RF module Destination Address (Low) to “0x1F”. To store the new value to non-volatile (long term) memory, subsequently send the WR (Write) command. For modified parameter values to persist in the module’s registry after a reset, changes must be saved to non-volatile memory using the WR (Write) Command. Otherwise, parameters are restored to previously saved values after the module is reset.

System Response

 

When a command is sent to the module, the module will parse and execute the command. Upon successful execution of a command, the module returns an “OK” message. If execution of a command results in an error, the module returns an “ERROR” message.

To Exit AT Command Mode:

 

1. Send the ATCN (Exit Command Mode) command (followed by a carriage return).

2. If no valid AT Commands are received within the time specified by CT (Command Mode

Timeout) Command, the RF module automatically returns to Idle Mode.

6.8.1 AT Commands Description:

 

SH (Serial Number High) Command

 

The SH command is used to read the high 32 bits of the RF module’s unique IEEE 64-bit address. The module serial number is set at the factory and is read-only.

AT Command: ATSH

Parameter Range: 0 – 0xFFFFFFFF [read-only]

Related Commands: SL (Serial Number Low), MY (Source Address).

SL (Serial Number Low) Command

 

The SL command is used to read the low 32 bits of the RF module’s unique IEEE 64-bit address. The module serial number is set at the factory and is read-only.

AT Command: ATSL

Parameter Range: 0 – 0xFFFFFFFF [read-only]

Related Commands: SH (Serial Number High), MY (Source Address)

 

DH (Destination Address High) Command

The DH command issued to set and read the upper 32 bits of the RF module’s 64-bit destination address. When combined with the DL (Destination Address Low) parameter, it defines the destination address used for transmission.

A module will only communicate with other modules having the same channel (CH parameter); PAN ID (ID parameter) and destination address (DH + DL parameters).

To transmit using a 16-bit address, set the DH parameter to zero and the DL parameter less than 0xFFFF. 0x000000000000FFFF (DL concatenated to DH) is the broadcast address for the PAN.

AT Command: ATDH

Parameter Range: 0 – 0xFFFFFFFF

Default Parameter Value: 0

Related Commands: DL (Destination Address Low), CH (Channel), ID (PAN VID)

DL (Destination Address Low) Command

 

The DL command is used to set and read the lower 32 bits of the RF module’s 64-bit destination address. When combined with the DH (Destination Address High) parameter, it defines the destination address used for transmission. A module will only communicate with other modules having the same channel (CH parameter), PAN ID (ID parameter) and destination address (DH + DL parameters).

To transmit using a 16-bit address, set the DH parameter to zero and the DL parameter less than 0xFFFF. 0x000000000000FFFF (DL concatenated to DH) is the broadcast address for the PAN.

AT Command: ATDL

Parameter Range: 0 – 0xFFFFFFFF

Default Parameter Value: 0

Related Commands: DH (Destination Address High), CH (Channel), ID (PAN VID)

DN (Destination Node) Command

 

The DN command is used to resolve a NI (Node Identifier) string to a physical address. The following events occur upon successful command execution:

1. DL and DH are set to the address of the module with the matching NI (Node Identifier).

2. ‘OK’ is returned.

3. RF module automatically exits AT Command Mode.

If there is no response from a modem within 200 msec or a parameter is not specified (left blank), the command is terminated and an ‘ERROR’ message is returned.

AT Command: ATDN

Parameter Range: 20-character ASCII String

Minimum Firmware Version Required: v1.x80

BD (Interface Data Rate) Command

 

The BD command is used to set and read the serial interface data rate used between the RF module and host. This parameter determines the rate at which serial data is sent to the module from the host. Modified interface data rates do not take effect until the CN (Exit AT Command Mode) command is issued and the system returns the ‘OK’ response.

When parameters 0-7 are sent to the module, the respective interface data rates are used. The RF data rate is not affected by the BD parameter. If the interface data rate is set higher than the RF data rate, a flow control configuration may need to be implemented.

AT Command: ATBD

Parameter Range: 0 – 7 (standard rates) 0x80-0x1C200 (non-standard rates)

Table: 6.6 Setting Different Baud Rate

Parameter	Configuration (bps)
0	1200
1	2400
2	4800
3	9600
4	19200
5	38400
6	57600
7	115200

Default Parameter Value: 3

CE (Coordinator Enable) Command

 

The CE command is used to set and read the behavior (End Device vs. Coordinator) of the RF module.

AT Command: ATCE

Parameter Range: 0 – 1

Table: 6.7 Configuring the RF Module

Parameter	Configuration
0	End device
1	Coordinator

Default Parameter Value: 0

Minimum Firmware Version Required: v1.x80

CH (Channel) Command

 

The CH command is used to set/read the operating channel on which RF connections are made between RF modules. The channel is one of three addressing options available to the module. The other options are the PAN ID (ID command) and destination addresses (DL & DH commands).

In order for modules to communicate with each other, the modules must share the same channel number. Different channels can be used to prevent modules in one network from listening to transmissions of another. Adjacent channel rejection is 23 dB.

The module uses channel numbers of the 802.15.4 standard.

Center Frequency = 2.405 + (CH – 11d) * 5 MHz   (d = decimal)

AT Command: ATCH

Parameter Range: 0x0B – 0x1A (XBee) 0x0C – 0x17 (XBee-PRO)

Default Parameter Value: 0x0C (12 decimal)

Related Commands: ID (PAN ID), DL

(Destination Address Low, DH (Destination Address High)

ID (Pan ID) Command

 

The ID command is used to set and read the PAN (Personal Area Network) ID of the RF module. Only modules with matching PAN IDs can communicate with each other. Unique PAN IDs enable control of which RF packets are received by a module.

Setting the ID parameter to 0xFFFF indicates a global transmission for all PANs. It does not indicate a global receives.

AT Command: ATID