Built In Self Testing For SOC’s

ABSTRACT

Testing of circuits with external testing equipment is becoming very difficult due to the manual interface between the VLSI design and performance of the external tester. Hence, external testers are less efficient due to increasing cost and high yield loss which causes inherent testing accuracies. To overcome the inaccuracies caused by the external testers, the processor should empower to test by itself. Hardware based built in self-testing methodologies have many drawbacks due low performance issues and inabilities in structural testing to generate random test patterns with low fault coverage.

Software based built in self-testing methods are under review and are being developed in the research field to overcome the problems with the hardware testing equipment. In this process of testing, programmable cores are used for software based built in self-testing on processors for generating test patterns as inputs for testing to analyse the output response and also to detect and diagnose the faults present in the processor.  Once the programmable core tests itself on the processor, it can be used again for testing buses and global interconnects and other non-programmable IP cores.[1] The benefits of this techniques are at- speed testing, high performance testing, low yield loss, high fault coverage, low cost modelling, less hardware utilization and easy generation of random test patterns. In this paper, we give a literature survey of the techniques which can be applied on circuits and challenges emerging in the software based built in self testing paradigm.

1.0 INTRODUCTION

Usage of testing circuits on recent VLSI Chips has many drawbacks with respect to yield, time, speed and cost. Recently used testing circuits cannot be relied upon due to the increasing complexity and decreasing size of the chips. The current testing circuits cannot be used on the upcoming new circuits due to rapid variation of speed and performance between the circuits and testers. Software based built in self testing is implemented on machines rather than computers. The industries these days, install the self-testing software in the devices or machines to control and manage by itself. Mostly, the embedded software is specially designed for a typical hardware design. There are different types of embedded software used for complex hardware which, need the requirement of crucial development of software based built in self testing. Hence, Embedded Software Developers are developing automatic testing tools to test and detect the faults in the chips. The main motivation behind this research is to increase the efficiency of testing by controlling the increasing yield loss to an acceptable rate. To overcome the above issues, a software based built in self testing equipment will be proposed.[6]

The architecture of SOCs has been widely used due to a large number of components present in a single silicon chip such as ADC, DAC, mixed signals, RF signals and systems such as micromechanical on a single silicon chip. The programming abilities of SOCs along with its architecture with high operating frequencies and change in the technology is improvising the VLSI testing methodologies. Due to the growing gap between the performance of the external tester and the speed of the device, there are many challenges faced by the external testers such as high yield loss which cause errors in the output response and lead to loss of good chips, high speed external testers are not cost efficient as they are very costly, mixed signal testing with analogue components cannot be tested on a digital logic tester and vice versa. And also, testing a mixed signal component with a mixed signal chip would be a very expensive form of VLSI testing.

Software based built in self testing techniques eliminate the requirements of external testers and has the provision to apply the input test signal and analyse the output response with at speed which provide good precision than the external tester. Already existing built in self testing methodologies use the structural form of testing techniques. The scan based built in self testing methodologies is a form of the structural built in self testing which provides good quality test results and depends on a dedicated hardware circuit for testing. Due to the dedicated hardware circuit dependency in testing, there is an area, performance and time overhead. Structural built in self testing applies structural random testing patterns which cause increase in power consumption compared to normal system operations. [3]Also, existing external testers follow structural built in self testing methodologies which lead to difficulty in diagnosing and detecting time related faults. In addition, the existing structural built in self testing techniques require the solutions to resolve the problems related to various timing issues.

A new software based built in self testing equipment can overcome the problems occurring in the external testers and hardware based built in self testing. The software based built in self testing consists of programmable cores on the processor which first tests itself by compiling and executing an automatically synthesised random test program which can diagnose and detect high fault coverage. The software based built in self testing technique uses the structural random testing pattern as its strategy in the VLSI design environment. Hence, this eliminates the problems caused by the functional testing patterns in the VLSI design environment. Then, the programmable core generates the random testing pattern and also analyses the output response of processors on busses and global interconnects and other non-programmable IP cores. This technique is also known as structural built in self testing.

The concept on software based built in self testing is illustrated in Figure 1 using busses and global interconnects on the processor. The non-programmable IP cores in the processor are connected to A PCI bus and global interconnect via VCI. The Virtual Component Interface establishes a communication between the non-programmable IP core and the bus and global interconnect. Firstly, the chip tests itself by compiling and running a set of automatically synthesised program. Then, the chip tests the busses and global interconnects and other non-programmable IP cores in the processor. To support the software based built in self testing technique, the non-programmable IP core consists of a test wrapper surrounding it. The test wrapper has the test support logic required to manage at speed testing. Therefore, the processors bus shares the bus and the and the control access with the bus and global interconnects.[2,5]

There are many benefits in using the software based built in self testing techniques. Firstly, it permits to use the software equipment on the processor multiple times which eliminates the use of hardware dedicated circuit. Secondly, this helps to eliminate the requirement for very costly at speed external testers which are not cost efficient and also decreases the yield loss due to the problems on lack of precisions while testing. Software based built in self testing provides the feature to apply random testing pattern and analyse the output response against the at speed external tester which gives better precision than the existing external testers.  Lastly, the hardware based built in self testing applies the structural methodology of built in self testing to operate in a normal mode of the VLSI design environment. Also, the random test pattern is applied in the form of automatically synthesised program for testing the processor. This leads to the elimination of the problems caused due to the structural random testing patterns which results in very high-power consumption when hardware based built in self testing is used.

Thus, structural built in self testing can eliminate the delays occurring during testing. The Delay occurred during testing uses the scan methodologies which operates at a lower frequency to make DFT implementation possible. After all the states are scanned, the system generates two or more clock cycles. The first clock cycle is the launch clock cycle which passes the output of all states to the combinational block. The second clock cycle is the capture clock cycle which takes the response back to scan for testing.[8] During the first cock cycle and the second clock cycle, there circuit is affected by delays due to increase the increase in surge of current.  The increase in clock cycle will not always result in reducing the delay. Another strategy which can be used to reduce delay is to use multiple clock cycles after scanning which may lead to stabilization of power. This process needs a greater number of clock cycles which causes problems in Automatic Test Pattern Generation.

Structural built in self testing can also reduce problems caused by functional test patterns during structural delay testing with scanning or built in self testing may lead to increasing yield loss and over testing.  Experimental results have shown that functional self-testing results in delay faults in the processor and structural testing methodology of a circuit is never sensitive to faults. Thus, no faults are present in the output response of the structural circuit. The defects diagnosed on these faults never affect the performance of the self-testing equipment which does not require testing. Analog components needed to be tested is a very costly process due to its limited parts in the external testers requiring structural testing. The scenario has led to worst situation because of combining the analogue components and digital components on a single processor. The testing of ADC and DAC signals with the software based built in self-testing equipment eliminates the problems of testing by introducing the digital signal processing strategy.

In this paper, we are giving a literature survey of the software based built in self-testing techniques. We are introducing by explaining the delay faults and stuck at faults. Then we are continuing the paper by discussing the software based built in self testing methodologies of busses and global interconnects and also other non-programmable IP cores on processor. We are also explaining the instruction level Design for Testability strategy which applies the automatically generated testing program to increase the fault coverage and decrease the testing time and program size. Lastly, we summarize the Digital Signal Processing based built in self testing for ADC and DAC components.[9]

3.0 DISCUSSION

3.1 SELF TESTING OF CHIPS

While logical built in self-testing is widely used in industrial purposes on specific ICs, it is not efficient on processors. Firstly, the changes needed for making a BIST processor immune to problems such as bus interconnects when random test patterns are applied should accept any cost in manual efforts and significant performance degradation. Also, processors are resistant to random test patterns. Thus, the chip does not accept the random test patterns due to the critical timing nature of the chip which is a problematic issue and also there could be a degradation in the performance. The Built in Self Testing determined till date has led to unacceptable are overhead which states that the size of the hardware processor to determine the random test pattern depends on the ability of the circuit testing [9].

Several approaches were proposed to generate structural tests for chips. For some, these proposals were opposed and the external testers [10] have still been used for testing and for others the chips were allowed to test themselves by using the self-testing programs. The most common methodology used with all these properties [11] is an application of the program with random test patterns given to the chip under test. Although the chips are more compatible with the random test instructions than the random test patterns, it is very difficult to achieve structural faults by applying random test instructions at the processor level. There were techniques made in [13] [14] using the structural Automatic Test Pattern Generation to generate tests for stuck at faults in the chip. They use the Register Transfer Level data of the chip to form a set of Register Transfer Level modules that can detect the gate level testing generated. Solving these modules specifies the needed program sets of all the operands. All the above strategies achieve only the stuck at faults and also these techniques cannot be used to easily detect the delay faults.

Unlike the hardware based built in self-testing, the software based built in self-testing is non-intrusive as it applies the random test pattern in the normal operational mode to the processor. Therefore, the software programs have the features of guiding the random test patterns through a complex chip, avoiding the component blocks of the random test instruction to structural controlling signals as in the case of hardware based logical Built in Self Testing.

The software based Built in Self Testing techniques for chips have been proposed [4] [5] [6]. The techniques contain the main step of test preparation and the self-testing. The step containing the test preparation involves the generation of the test realization for the block components of the chip. The test Realization can be delivered using the program. Thus, to avoid the result of the random test patterns which were not delivered, the tests are conducted under certain limitations of the chip data sets. The tests can either be stored or generated on the processor relying on the technique used which is much more efficient for all the cases. The low speed external tester is used to load the self-testing values and to predetermine the tests to be done to the chip memory before applying the test.

Figure 1: Embedded software based self-testing system[1]

The step of self-testing is applying these random test patterns using the software based built in self-testing. The software based built in self-testing reduces the results into self-testing values that can be stored into the memory. The values can later be retrieved and analysed by the external testers. The chip memory has been tested with the normal methods such as memory of the Built in Self Testing prior to applying the test and memory to be free from all faults. Hereafter, the software based built in self-testing strategy will be discussed to detect the stuck at [4] faults and path delay faults [5] [6] in the chips with the set of programs.

The first step of the Stuck at Fault Testing is the test realization of the structural tests for the block components of the chip which are being processed. The block Component tests is either stored or conducted on a processor. If the tests are conducted on the processor then the tests require the components of each and every property by a self-testing value which includes the random test number produced as the count of random test patterns to be produced. The built-in self-testing values is expanded on the processor into the test instructions using the random test number generation code. Many built in self-testing values can be used for each block component when required. Hence, the built-in self-testing techniques permits the combination of determining the Built in Self Testing strategies that determine the test instruction as many random test pattern instructions [15] [16].

Achieving the structural test requires simple block components from the proposed technique which has a very high advantage of determining the fault coverage with structural testing. Applying the block component test and collecting the output results are performed with codes instead of scanning which does not need any performance overhead or area overhead and also by applying the tests performed at speed. Therefore, by analysing the features of the external testers in the application of test instructions and releases the outputs which permits the at speed testing of GHz chips with low speed external testers [17].

For the Delay Testing the test program is synthesized for built in self-testing of the path delay faults in a chip using its data codes in which first the constraints between the register transfer level and the control signals are obtained. Then, the delay path property [18] [19] is examined by all the paths and path segments. If the path and the path segment can never be sensitized with the obtained constraints, the path is structurally not untestable which eliminated all the faults. Therefore, this has the advantage of reducing the complicated computational efforts during the testing procedure [5]

Then, the long large delay paths among the structural testing delay parts are selected to achieve the necessary test conducted. A gate level Automatic Test Pattern Generation for the path delay faults obtains the constraints on the testing procedure and is used to achieve the path delay faults. If the test is conducted successfully, it sensitizes the path delay faults and obtains the constraints. Thus, the program code is delivered. The procedure of the test code is synthesized which follows the specific values at flip flops to values in register transfer level and values at control signals. These values need justification at the data level. At last, the procedure is used to detect and diagnose the path fault delays in the register transfer level of the flip flops of the path delay faults the memory. This procedure combines the details of all the registers in the chip which conducts the values and stores it in the memory. The routine is repeated over and over again till all the path delay faults processed have been achieved. The test code is conducted and then later on used to test the chip at speed.

Applying the test code to synthesize loads the on-processor memory by a low speed external tester. Then the test code is executed at speed by recording the set of values in memory. At last of the test code, the output is combined to record the values in the memory and to finally compare the combined values with the correct values.

3.2 INSTRUCTION LEVEL DFT:

While self-testing manufacturing defects in an SOC by running test programs in IP core has many potential benefits but this strategy might require a length test program and might not achieve a high fault coverage. Self-testing for manufacturing defects in an SoC by running test programs on IP core has many potential advantages, but such a self-test strategy might require a lengthy  test program and might not achieve a high enough fault coverage. These problems can be overcome by applying DFT methodology , this methodology adds test instructions to an on-chip programmable cores such as a microprocessor core. This methodology is called instructive-level DFT.

Self-testing to find the manufacturing hardware defects on an system on chip by running testing code on a programmable cores has many advantages, such a  self-testing techniques requires a very lengthy test code and this may not achieve a very high fault coverage. These problems can be eliminated by applying a design for testability techniques. In this DFT methodology, test instructions are added to an on-chip programmable processor, this methodology is called as instruction-level DFT.

Instruction level design for testability adds testing circuitry this circuitry adds testing codes which is less intrusive approach when compared to gate level design for testability. In gate level DFT a separate test mode is somewhat orthogonal to the functional mode. when the test instructions are carefully designed such that their micro code instructions reuse the data path for the functional instructions and do not require any new datapath.

The instruction level DFT which was introduced in [11]b introduces instructions to control interrupts and reset exceptions. With new code of instructions test code has higher fault coverage of around 87% to 90% for struck at faults but it cannot achieve higher fault coverage because the test code generated based on random approach which do not have a overall control over some internal registers that have low testability.

The design for testability which was introduced in [27] provides test codes to processor on system on chip systematically. As a result it will reduce the overall test code and even reduces the run time there by increasing the self-testability of a processor core. After analyzing the processor testability the precise instructions are added for example if a particular register is found to be hard to access then a instructions which gives direct access to the registers are added to the test code. Moreover optimizing the testing code and its run time can be done just by introducing test code instruction.

Giving test code instructions to the programmable cores does not increase the testability of non programmable cores on system on chips and thereby it cannot increase the fault coverage of non-programmable cores. Giving testing codes for non-programmable cores is the only solution to optimize the non-programmable cores i,e the same  set of test pattern are used for both non-programmable and programmable cores on system on chips. By analyzing the experimental outputs of the two processors in (parwan[17] and dlx [20]) gives an overview that the test instructions will optimize the the program size and its run time by 20% and the cost by 1.6% area overhead [1].

 

3.3 SELF-TESTING OF OTHER NON-PROGRAMMABLE IP CORES:

Testing non-programmable cores on a system-on-chip are complex and have many unresolved problems [25]. The industry has taken many initiatives such as the IEEE P1500 working group [26] provides some solutions for IP core testing, but this initiative does not address the requirements of at-speed testing.

A self-testing methodology for non-programmable cores on system on chips has been proposed in [25]. Test program provides the desired test patterns for the IP cores in the soc at speed. The test program which is stored in embedded processor are either generated on the processor or fetched from an external ATE (automatic test generator). The on-chip pattern generator alleviates the need for dedicated external circuitry for pattern generation as well as to analyze the output response. This technique is even applicable to large size IP cores whose structural netlist are available. Moreover, this methodology can even support delay tests as pattern delivery is done at the SOC operational speed [1].

Figure 2: The test flow

The test flow for the embedded software self-testing approach is shown in the figure fig(). This test flow is divided into two phases pre-processing phase and a testing phase. This test flow has a greater advantage as this methodology offers very good flexibility in the type of tests which are applied for IP cores as it provides a desired quality of test patterns without any hardware overhead.

In the first phase i,e pre-processing phase, a tests test wrapper is inserted around the IP core which is under test. The test wrapper are programmed to meet the specific testing which is needed for the IP cores. After each scan sequence, various test patterns are generated using multiple weight sets or by using multiple capture cycles [3]. In the next step, a high-level test program is created which synchronizes the software pattern generation, the start of the application test and analyzing the test response. The program can further synchronize multiple testing cores in parallel. Further, the test program is then compiled to generate a processor-specific binary code.

In the second phase, the testing program which is running on the embedded processor core is used to test various IP cores.  The processor sends the test packet to the IP core test wrapper informing the wrapper about the test application scheme. The test wrapper provides the necessary scan shifts and captures the output response. The output response is stored in the PI/PO and scan buffers, the processor core then reads the output from buffers.

3.4 TESTING OF BUSES AND GLOBAL INTERCONNECTS

Core to core communication is a very important part of the SOC design. In order to achieve high performance, good interconnect performance is required. As the mutual inductance and cross coupling capacitance increases the interference between signals increases resulting in loss of signal integrity and increase in delay. Here we are talking about a BIST method where hardware pattern generators and error detectors are used to check for crosstalk defects in SOC’s interconnects.  In normal operation mode not all test patterns are valid. A few test patterns may result in more loss in yield. In the  proposed system, procedure is programming based and empowers an embedded processor  in SoC to test for crosstalk impacts in these interconnects by executing a product program.[1] The system is to give the processor a chance to execute an individual test program with which the test vector sets can be connected to the suitable transport in the ordinary useful method of the framework. Within the sight of crosstalk delay and  glitches induced , the second vector in the vector match at the receiver end is distorted. This error can be stored as a test response in the memory and can be used for off chip analysis in later stage.

3.4.1 Databus testing

In a bi directional bus, the crosstalk tests have to be conducted in both the directions. If we consider a vector pair (v1,v2) for testing, the data is first sent to from the vector v1 to the core. The direction of data flow can be from v1 to core or from core to v1. Next when data from v2 is received it analyses that data. The data can be directly stored to the memory if that is the core. If not more instructions have to be executed to read thata data.[7]

3.4.2 Address bus testing

The address bus is a unidirectional bus. Hence to read the data from both the vectors v1 and v2 they have to be sent to the CPU in  a consecutive order. In a non-memory core as the core is addressed by the CPU through memory-mapped I/O, the address present in the core must be v1.Sometimes when the crosstalk is distorted, wrong address will be received by the CPU. This address may be related to some other core or physical memory. By storing these 2  different data in 2 different vectors, it can continue with the analysis.

3.5 TESTING OF ON CHIP ADC/DAC AND ANALOG COMPONENTS

All mixed signal and analog circuits tested functionally for which expensive ATE are required for stimulus generation of analog signals. Embedded based software tests are performed to check generation, tests and analysis of the response obtained. Requirements for external tests are the most part of BIST testing. Due to the advancements in CMOS technology BIST came into demand. It was very much required solution for testing analog and mixes signals digitally and get exact results.

In our paper we talk about an efficient system for testing on-chips. Delta-sigma modulation method is used for the stimulus generation and analysis of the responses. In on-chip generated tests the self test data derived as result of test preparation is expanded into subsets using the false number generator.

Figure 3: DSP based self-test

The above figure shows the Delta-sigma modulator system which convers the signals to one bit. One-bit DAC converts 1’s and 0’s to 2 discrete levels.Then the original waveforms are restored using the low pass filter which eliminates noise with high frequency.

Practically speaking, a segment is extracted from the delta-sigma result which contains many signals.  The on-chip memory stores the generated patterns which are used to derive the required stimulus by applying them on the Low pass filter and DAC. Correspondingly, for analyzing the response, a 1-bit Σ−∆ modulator can be embedded to change over the simple DUT yield reaction into a 1-bit stream which is then  studied by the DSP tasks performed by on-chip DSP. First order configuration has maximum dynamic range among the one-bit modulators. It cannot be used for all kinds of high resolution analysis because of its distortion problems. Second order configuration has less dynamic range compared to first order but can be mostly used for higher resolution.

3.6 EMBEDDED TEST FOR MEMORY CORES:

In future all the embedded systems are expected to have a very densely arranged memories of about 256 bits or may be larger on a very small chip area. The memories may include SRAM, DRAM and FLASH memories. Most of the memories today have built in self-testing in their memory designs. The memories are dependent on the embedded cores for input test signals. The sink in the memory not only evaluates the memory response data but also diagnosis’s the failed bits [18][19].

Defects in the memory layout is fault modeled and latter these defects are first analyzed and classified resulting in SRAM cell level fault model. The resulting defects  in the circuits are may be due to breaks and shorts in the circuits [20][21].

The data and address buses are used in testing process i,e the test patterns which are stored in processor uses data and address buses for delivering the test code signals for memory. In memory testing, only deterministic test patterns are used.

4.0 SIMULATIONS AND RESULTS

Figure 4: Maximum Aggressor tests results

In order to model crosstalk defects on global interconnects a fault model named Maximum Aggressor is used. Faults are defined in this system using crosstalk errors which include positive glitch (gp), negative glitch (gn), rising delay (dr) and falling delay (df). When a set of number of interconnects N are present, only a wire Yi is selected by the fault model and all other wires are considered as aggressors. Figure 1 shows the transition for the 4 types of errors for different wires.

Though this method overcomes all errors due to crosstalk, due to the constraints present in them they tend to not occur in regular system operation. Hence a functionally maximum aggressor test method can be used. Here from the bus a test program is sent to the processor core and at the other end of the bus the buffer from the destination core collects the responses. To check for the occurrence of faults these reponses have ton be read by the processor  core again. As the processor core cannot read the non-memory core inputs a DFT can be used for the valuation.

Figure 5: Fault for different phases

We have done analysis on two different faults. They are stuck at fault and delay fault.Tests are performed on different on-chip test patterns and the results are obtained.Graph above shows the yield estimations of C1 and C2 for stages Φ0- Φ5. The estimation of f_test is zero amid stages Φ1 and Φ2, constraining the control point C1 to be zero independent of the estimation of f. Be that as it may, amid stages Φ0 and Φ3, f_test’s esteem is 1 and the typical flag f is passed to C1. Likewise, g_test’s esteem is one amid stages Φ2 and Φ3 compelling the yield of C2, paying little heed to g’s esteem, to one. Amid Φ0 and Φ1, g_test is zero, enabling the typical flag g to come to the yield of C2.

Control focuses that are enabled in a similar stage share the signals of the next stage. This is represented by the sharing of Φ2 yield of the stage decoder between control focuses C1 and C2. Consequently sharing of control points indicates that it is driven by logic. After the completion of selection of control points, this sharing is done in traditional methods. The control point is more involved compared to observation point. Fanout from different nodes help in the implementation of observation point. Either space comparator or output analyzer are connected to the fanout directly.

6.0 CONCLUSION

Software based built in self testing has the ability to eliminate the existing external testers and hardware based built in self testing methodologies for processors. In this paper, we are summarizing the recently introduced strategies for software based built in self testing for processors. The main aim in implementing these strategies is to derive testing constraints. Future research in this field must illustrate the problems with the existing testers and the solution to implement the above strategies.

7.0 FUTURE SCOPE

The future research and development in embedded based built in self-testing addresses the problems of extracting the test constraints i,e automating the constraint extraction process. Embedded based built in self testing for analog/mixed-signal components can be generalized by integrating DSP based testing techniques.

CONTRIBUTIONS OF EACH MEMBER

Kiruthikaa Balu :

• Analysed the stuck at fault and path delay faults in processors using their instruction sets and studied the usage of software based self-testing on the processor in overcoming to build different circuits of BIST for testing.
• Made a detailed study on Software based testing tools which are used for hardware testing till date and suggesting other improvisation techniques and performed analysis.

Priyanka Sri Ramasetty

• Analysed Software-based self-testing which tests its own interconnects for cross-talk defects using on-chip hardware pattern generators and error detectors. Performed Maximum fault model analysis and obtained test results.
• Studied about DSP bases self-test system for on-chip ADC/DAC and analog components and how BIST has become the best solution for these problems.

Vinay Kumar Reddy Manikyam

• Studied in detail the methods to implement the Instruction Level DFT in software based self-testing on hardware processor which reduces the size and run time of the programming code.
• Analysed the test flow patterns of  Self-Testing of other non-programmable IP cores which are used to support pattern delivery which contains test logic to store scanned data and support at-speed test.

REFERENCES

[1] C.-J. Lin, Y. Zorian, and S. Bhawmik. Integration of Partial Scan and Built-in Self-Test. JETTA, Aug. 1995.

[2] H.-C. Tsai, S. Bhawmik, and K.-T. Cheng. An Almost Full-Scan BIST Solution – Higher Fault Coverage and Shorter Test Application Time. ITC, 1998.

[3] K.-T. Cheng and C.-J. Lin. Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. ITC, 1995.

[4] L. Chen and S. Dey. Software-Based Self-Testing Methodology for Processor Cores. TCAD, Mar. 2001.

[5] K.-T. Cheng W.-C. Lai, A. Krstic, On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. VTS, 2000.

[6] W.-C. Lai, A. Krstic, and K.-T. Cheng. Test Program Synthesis for Path Delay Faults in Microprocessor Cores. ITC, 2000.

[7] On-Chip Bus Development Working Group. Virtual Component Interface Standard (OCB 2 1.0), Mar. 2000.

[8] On-Chip Bus Development Working Group. Virtual Component Interface Standard (OCB 2 1.0), Mar. 2000.

[9] G. Kiefer, H. Vranken, E. J. Marinissen, and H.-J. Wunderlich. Application of Deterministic Logic BIST on Industrial Circuits. ITC, 2000.

[10] R. Rajsuman. Testing A System-on-Chip with Embedded Microprocessors. ITC, 1999.

[11] J. Shen and J. A. Abraham. Native Mode Functional Test Generation for Processors with Applications to Self Test and Design Validation. ITC, 1998.

[12] Z. Navabi. VHDL: Analysis and Modeling of Digital Systems. McGraw-Hill, New York, 1997.

[13] M. Gumm. VHDL – Modeling and Synthesis of the DLXS RISC Processor. VLSI Design Course Notes, Univ. of Stuttgart, Germany, Dec. 1995.

[14] W.-C. Lai and K.-T. Cheng. Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. DAC, 2001.

[15] H.-C. Tsai, S. Bhawmik, and K.-T. Cheng. An Almost Full-Scan BIST Solution – Higher Fault Coverage and Shorter Test Application Time. ITC, 1998.

[16] J.-R. Huang, M. K. Iyer and K.-T. Cheng. A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS, 2001.

[17] IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/.

[18] Zorian, Y. “System-Chip Test Strategies,” Proceedings of the 35th Design Automation  Conference, pp 752-757,

(1998).

[19] Zorian, Y. Dey, S. and Rodger, M. J. “Test of Future System-on-Chip,” Proceedings of the International Conference on Computer-Aided Design, pp 392-398, (2000).

[20] Dekker, R. et al. “A Realistic Fault Model and Test Algorithm for Static Random Access Memories,” IEEE

Trans. On CAD, 9(6), pp 567-572, (1990).

[21] Dekker, R. et al. “Fault Modeling and Test Algorithm Development for SRAMs,” Proceedings of the

International Test Conference (ITC), pp 343-351, (1988).